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em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 1 www.emmicroelectronic.com ultra low power microcontroller with 4x8 lcd driver features ? low power - 2.1 a active mode, lcd on - 0.5 a standby mode, lcd off - 0.1 a sleep mode @ 1.5v, 32khz, 25c ? low voltage - 1.2 to 3.6 v ? svld - metal mask programmable (2.0v) ? rom - 1280 16 bits ? ram - 64 4 bits ? 2 clocks per instruction cycle ? 72 basic instructions ? oscillation supervisor ? timer watchdog (2 sec) ? max. 8 inputs ; port a, port b ? max. 4 outputs ; port b ? lcd 8 segments, 3 or 4 times multiplexed ? universal 10-bit counter, pwm, event counter ? prescaler down to 1 hz (crystal = 32 khz) ? 1/1000 sec, 12 bit binary coded decimal counter with hard or software start/stop function ? frequency output 1hz, 2048 hz, 32 khz, pwm ? 7 internal interrupt sources (bcd counter, ? 2 10-bit counter, 3 prescaler, svld) ? 5 external interrupt sources (port a, compare) description the em6620 is an advanced single chip cmos 4- bit microcontroller. it contains rom, ram, power on reset, watchdog timer, oscillation detection circuit, 10 bit up/down counter, millisecond counter, prescaler, voltage level detector (svld), compare input, frequency output, lcd driver and several clock functions. the low voltage feature and low power consumption make it the most suitable controller for battery, stand alone and mobile equipment. the em6620 is manufactured using em microeletronic?s advanced low power (alp) cmos process. typical applications ? timing device ? medical applications ? domestic appliance ? timer / sports timing devices ? safety and security devices ? automotive controls with display ? measurement equipment ? interactive system with display ? bicycle computers figure 1. architecture figure 2. pin configuration em microelectronic - marin sa
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 2 www.emmicroelectronic.com em6620 at a glance ? power supply - low voltage low power architecture including internal voltage regulator - 1.2 ... 3.6 v battery voltage - 2.1 a in active mode (xtal, lcd on, 25 c) - 0.5 a in standby mode (xtal, lcd off, 25 c) - 0.1 a in sleep mode (25 c) - 32 khz oscillator ? ram - 64 x 4 bit, direct addressable ? rom - 1280 x 16 bits, metal mask programmable ? cpu - 4 bit risc architecture - 2 clock cycles per instruction - 72 basic instructions ? main operating modes and resets - active mode (cpu is running) - standby mode (cpu in halt) - sleep mode (no clock, reset state) - initial reset on power on (por) - watchdog reset (logic and oscillation watchdogs) - reset with input combination on port a (register selectable) ? liquid crystal display driver (lcd) - 8 segments 3 or 4 times multiplexed - internal or external voltage multiplier - free segment allocation architecture (metal 2 mask) - lcd switch off for power save ? 4-bit input port a - direct input read on the port terminals - debouncer function available on all inputs - interrupt request on positive or negative edge - pull-up or pull-down or none selectable by register - test variables (software) for conditional jumps - pa[0] and pa[3] are inputs for the event counter - pa[3] is start/stop input for the millisecond counter - reset with input combination (register selectable) ? prescaler - 15 stage system clock divider down to 1hz - 3 interrupt requests; 1hz, 32hz or 8hz, blink - prescaler reset (4khz to 1hz) ? 4-bit bi-directional port b - all different functions bit-wise selectable - direct input read on the port terminals - data output latches - cmos or nch. open drain outputs - pull-down or pull-up selectable - weak pull-up in nch. open drain mode - selectable pwm, 32khz, 1khz and 1hz output - dynamic input comparator on pb[0] (svld level) ? voltage level detector - mask selectable level, default 2.0v - busy flag during measure - interrupt request at end of measure ? 10-bit universal counter - 10, 8, 6 or 4 bit up/down counting - parallel load - event counting (pa[0] or pa[3]) - 8 different input clocks- - full 10 bit or limited (8, 6, 4 bit) compare function - 2 interrupt requests (on compare and on 0) - hi-frequency input on pa[3] and pa[0] - pulse width modulation ( pwm ) output ? millisecond counter - 3 digits binary coded decimal counter (12 bits) - pa[3] signal pulse width and period measurement - internal 1000 hz clock generation - hardware or software controlled start stop mode - interrupt request on either 1/10 sec or 1sec ? interrupt controller - 5 external and 7 internal interrupt request sources - each interrupt request individually maskable - each interrupt flag individually resettable - automatic reset of each interrupt request register after read - general interrupt request to cpu can be disabled - automatic enabling of general interrupt request flag when going into halt mode
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 3 www.emmicroelectronic.com table of contents features _________________________________1 description _______________________________1 typical applications _______________________1 em6620 at a glance ________________________2 1. pin description for em6620 _________ 4 2. operating modes ___________________ 6 2.1 active m ode ________________________6 2.2 standby m ode ______________________6 2.3 sleep m ode _________________________6 3. power supply ______________________ 7 4. reset _______________________________ 8 4.1 o scillation d etection c ircuit __________9 4.2 i nput p ort a r eset ____________________9 4.3 d igital w atchdog t imer r eset ________10 4.4 cpu s tate after r eset _______________10 5. oscillator and prescaler ________ 11 5.1 o scillator __________________________11 5.2 p rescaler __________________________11 6. input and output ports ___________ 13 6.1 p orts overview ______________________13 6.2 p ort a______________________________14 6.2.1 irq on port a ____________________14 6.2.2 pull-up/down _____________________15 6.2.3 software test variables______________15 6.2.4 port a for 10-bit counter and msc ___15 6.3 p ort a registers _____________________15 6.4 p ort b______________________________17 6.4.1 input / output mode _______________17 6.4.2 pull-up/down ____________________18 6.4.3 cmos / nch. open drain output ____18 6.4.4 pwm and frequency output _________19 6.5 pb[0] d ynamic i nput c omparator ______19 6.6 p ort b registers _____________________20 7. 10-bit counter _____________________ 21 7.1 f ull and l imited b it c ounting _________21 7.2 f requency s elect and u p /d own c ounting 22 7.3 e vent c ounting _____________________23 7.4 c ompare f unction ___________________23 7.5 p ulse w idth m odulation (pwm) _______23 7.5.1 how the pwm generator works.______24 7.5.2 pwm characteristics_______________24 7.6 c ounter s etup ______________________25 7.7 10- bit c ounter r egisters _____________25 8. millisecond counter ______________ 27 8.1 pa[3] i nput for msc _________________27 8.2 irq from msc_______________________27 8.3 msc-m odes _________________________28 8.4 m ode selection _____________________ 28 8.5 m illisecond c ounter r egisters _______ 30 9. interrupt controller ____________31 9.1 i nterrupt control registers __________ 32 10. supply voltage level detector _33 10.1 svld r egister ______________________ 33 11. ram ______________________________34 12. lcd driver _______________________35 12.1 lcd c ontrol _______________________ 36 12.2 lcd addressing _____________________ 36 12.3 f ree segment allocation _____________ 37 12.4 lcd r egisters ______________________ 37 13. peripheral memory map _________39 14. option register memory map ____42 15. active supply current test _____43 16. mask options ____________________44 16.1 i nput / o utput p orts _________________ 44 16.1.1 port a metal options ______________ 44 16.1.2 port b metal options ______________ 45 16.1.3 voltage regulator option___________ 46 16.1.4 svld and input comp level option __ 46 16.1.5 debouncer frequency option ________ 46 16.1.6 user defined lcd segment allocation _ 46 17. temp. and voltage behaviors ____47 17.1 idd c urrent ( typical ) _______________ 47 17.2 p ull - down r esistance ( typical ) _______ 47 17.3 p ull - up r esistance ( typical ) __________ 48 17.4 o utput currents ( typical )____________ 48 18. em6620 electrical specifications 49 18.1 a bsolute maximum ratings ___________ 49 18.2 h andling p rocedures ________________ 49 18.3 s tandard o perating c onditions _______ 49 18.4 dc characteristics - p ower s upply ____ 49 18.5 svld and i nput c omparator _________ 50 18.6 o scillator _________________________ 50 18.7 dc characteristics - i/o p ins _________ 51 18.8 lcd s eg [8:1] o utputs ________________ 52 18.9 lcd c om [4:1] o utputs _______________ 52 18.10 dc o utput c omponent _____________ 52 18.11 lcd voltage multiplier ____________ 52 19. pad location diagram ___________53 20. package & ordering information 54 20.1 o rdering i nformation _______________ 56 20.2 p ackage m arking ___________________ 56 20.3 c ustomer m arking __________________ 56 21. spec. update _____________________57 em microelectronic-marin sa cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an em microelectronic-marin sa product. em microelectronic-marin sa reserves the right to change the circuitry and specifications without notice at any time. you are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 4 www.emmicroelectronic.com 1. pin description for em6620 chip qfp 44 dil 40 qfp 32 signal name function remarks 1 13 7 9 c2b voltage multiplier not needed if ext. supply 2 14 8 10 c2a voltage multiplier not needed if ext. supply 3 15 9 11 c1b voltage multiplier not needed if ext. supply 4 16 10 12 c1a voltage multiplier not needed if ext. supply 5 18 11 13 vl1 voltage multiplier level 1 lcd level 1 input, if external supply selected 6 19 12 14 vl2 voltage multiplier level 2 lcd level 2 input, if external supply selected 7 20 13 15 vl3 voltage multiplier level 3 lcd level 3 input, if external supply selected 8 21 14 16 com[4] lcd back plane 4 not used if 3 times multiplex selected 9 25 17 17 com[3] lcd back plane 3 10 26 18 18 com[2] lcd back plane 2 11 27 19 19 com[1] lcd back plane 1 12 28 20 nc seg[8] lcd segment 8 not bonded for qfp 32 13 29 21 20 seg[7] lcd segment 7 14 30 22 21 seg[6] lcd segment 6 15 31 23 22 seg[5] lcd segment 5 16 32 24 23 seg[4] lcd segment 4 17 33 25 24 seg[3] lcd segment 3 18 35 27 25 seg[2] lcd segment 2 19 36 28 26 seg[1] lcd segment 1 20 37 29 27 test input test terminal internal pull-down 15k for em tests only, gnd 0 ! except when needed for mfp programming 21 38 30 28 pb[0] input/output, open drain port b terminal 0 port b data[0] i/o or dynamic input comparator input 22 39 31 29 pb[1] input/output, open drain port b terminal 1 port b data[1] i/o or ck[12] output 23 40 32 30 pb[2] input/output, open drain port b terminal 2 port b data[2] i/o or ck[1] output 24 41 33 31 pb[3] input/output, open drain port b terminal 3 port b data[3] i/o or pwm output 25 43 35 32 pa[0] input port a terminal 0 testvar 1 event counter 26 1 36 1 pa[1] input port a terminal 1 testvar 2 27 2 37 2 pa[2] input port a terminal 2 testvar 3 28 3 38 3 pa[3] input port a terminal 3 event counter msc start/stop control 29 5 39 4 vbat=vdd positive power supply mfp connection 30 6 40 5 vreg internal voltage regulator connect to minimum 100nf, mfp connection 31 8 1 6 qout / osc2 crystal terminal 32khz crystal, mfp connection 32 10 3 7 qin / osc1 crystal terminal 32khz crystal, mfp connection 33 11 5 8 vss negative power supply reference terminal, mfp connection * gray shaded : terminals needed for mfp programming connections (vdd, vreglogic, qin, qout, test, vss).
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 5 www.emmicroelectronic.com figure 3. typical configuration crystal lcd display c2 c2 c1 c1 c1 c4 c3 vreg vss test vdd (vbat) seg[8:1] qin qout c1a c1b c2a c2b com[4:1] vl1 vl2 vl3 port a port b em6620 all capacitors 100nf
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 6 www.emmicroelectronic.com 2. operating modes the em6620 has two low power dissipation modes, standby and sleep. figure 4 is a transition diagram for these modes. 2.1 active mode the active mode is the actual cpu running mode. instructions are read from the internal rom and executed by the cpu. leaving the active mode: via the halt instruction to go into standby mode, writing the sleep bit to go into sleep mode or detecting the reset condition from port a to go into reset mode. 2.2 standby mode executing a halt instruction puts the em6620 into standby mode. the voltage regulator, oscillator, watchdog timer, lcd, interrupts, timers and counters are operating. however, the cpu stops since the clock related to instruction execution stops. registers, ram and i/o pins retain their states prior to standby mode. standby is canceled by a reset or an interrupt request if enabled. 2.3 sleep mode writing to the sleep bit in the regsyscntl1 register puts the em6620 in sleep mode. the oscillator stops and most functions of the em6620 are inactive. to be able to write to the sleep bit, the sleepen bit in regsyscntl2 must first be set to "1". in sleep mode only the voltage regulator is active to maintain the ram data integrity, all other functions are in reset state. sleep mode may be canceled only by the input reset combination from port a . due to the cold-start characteristics of the oscillator, waking up from sleep mode may take some time to guarantee stable oscillation. during sleep mode and the following start up the em6620 is in reset state. waking up from sleep mode clears the sleep flag but not the sleepen bit. inspecting the sleepen allows to determine if the em6620 was powered up ( sleepen = "0") or woken from sleep mode (sleepen = "1"). take care !!! to quit sl eep mode, one must be sure to have a suitable defined combination of port a inputs for reset (see section 4.2). the bit noinpreset has no action during sleep mode. table 2.3.1 shows the state of the em6620 functions in standby and sleep modes function standby sleep oscillator active stopped oscillator supervisor active stopped instruction execution stopped stopped interrupt functions active stopped registers and flags retained reset ram data retained retained option registers retained retained timer/counter's active reset logic watchdog active reset i/o port b active high impedance, no pulls input port a active noinputres = "0" for reset generation only active for reset generation noinputres = "x" lcd active stopped (display off) voltage level detector finishes on going measure, then stop stopped figure 4 mode transition diagram active halt instruction sleep bit write irq standby sleep reset=1 reset=0 reset=1 reset=1 reset
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 7 www.emmicroelectronic.com 3. power supply the em6620 is supplied by a single external power supply between v dd (vbat) and v ss (ground). a built-in voltage regulator generates vreg providing regulated voltage for the oscillator and the internal logic. the output drivers are supplied directly from the external supply v dd . a internal power configuration is shown in figure 5. to supply the internal core logic it is possible to use either the internal voltage regulator (vreg < v dd ) or vbat directly ( vreg = v dd ). the selection is done by metal 1 mask option. by default the voltage regulator is used. refer to chapter 16.1.3 for the metal mask selection. the internal voltage regulator is chosen for high voltage systems. it saves power by reducing the internal core logic?s power supply to an optimum value. however, due to the inherent voltage drop over the regulator the minimal v dd value is restricted to 1.4v . a direct vbat connection can be selected for systems running on a 1.5v battery. the 1kohm resistor together with the external capacitor on vreg is filtering the v dd supply to the internal core. in this case the minimum v dd value can be as low as 1.2 v. figure 5. internal power supply ref. logic terminal vreg terminal vbat ref. lcd all pad input & output buffers, svld core logic, lcd logic, oscillator voltage m ultiplier, lcd outputs m1b m1a 1kohm mvreg
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 8 www.emmicroelectronic.com 4. reset figure 6 illustrates the reset structure of the em6620. one can see that there are five possible reset sources : (1) internal initial reset from the power on reset (por) circuitry. --> por (2) external reset by simultaneous high/low inputs to port a. --> system reset, reset cpu (combinations are defined in the registers optinprsel1 and optinprsel2 (3) internal reset from the digital watchdog. --> system reset, reset cpu (4) internal reset from the oscillation detection circuit. --> system reset, reset cpu (5) internal reset when sleep mode is activated. --> system reset, reset cpu all reset sources activate the system reset and the reset cpu. the ?system reset delay? ensures that the system reset remains active long enough for all system functions to be reset (active for n system clock cycles). the ?cpu reset delay? ensures that the reset cpu remains active until the oscillator is in stable oscillation. as well as activating the system reset and the reset cpu, the por also resets all option registers and the sleep enable ( sleepen ) latch. system reset and reset cpu do not reset the option registers nor the sleep enable latch. figure 6. reset structure system reset delay cpu reset delay enable a ctivate digital watchdog oscillation detection reset from port a input combination noinpreset sleep reset cpu inhibit oscillation detection inhibit digital watchdo g por por to option registers & sleep enable latch debounce sleep latch r sleep enable latch r por internal data bus write reset read status write active read status ck [ 10 ] ck [ 1 ] ck[8] ck[1] ck[15] por
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 9 www.emmicroelectronic.com 4.1 oscillation detection circuit at power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry, and thus the system reset. the cpu of the em6620 remains in the reset state for the ?cpu reset delay?, to allow the oscillator to stabilize after power up. the oscillator is disabled during sleep mode. so when waking up from sleep mode, the cpu of the em6620 remains in the reset state for the ?cpu reset delay? , to allow the oscillator to stabilize. during this oscillator stabilization period, the oscillation detection circuit is inhibited. in active or standby modes, the oscillator detection circuit monitors the oscillator. if it stops for any reason, a system reset is generated. after clock restart, the cpu waits for the cpu reset delay before executing the first instructions. the oscillation detection circuitry can be inhibited with nooscwd = 1 in register regvldcntl. at power up, and after any reset, the function is activated. the ?cpu reset delay? is 32768 system clocks ( ck[16] ) long. 4.2 input port a reset by writing the optinprsel1 and optinprsel2 registers it is possible to choose any combination of port a input values to execute a system reset. the reset condition must be valid for at least 16 ms (system clock = 32 khz) in active and standby mode. the applied port a reset condition will immediately trigger a system reset in sleep mode. bit noinputreset in option register optfselpb selects the input port a reset function in active and standby mode. if set to "0" the occurrence of the selected combination for input port a reset will trigger a system reset. set to ?1? the input port a reset function is inhibited. this option bit has no action in sleep mode, where the occurrence of the selected input port a reset combination will always immediately trigger a system reset. reset combination selection ( inpreset) in registers optinprsel1 and optinprsel2. inpreset = inprespa[0] inprespa[1] inprespa[2] inprespa[3] inpres1pa[n] inpres2pa[n] inprespa[n] 00v ss 0 1 pa[n] 1 0 not pa[n] 11v dd n = 0 to 3 i.e. ; - no reset if inprespa[n] = v ss . - don't care function on a single bit with its inprespa[n] = v dd . - always reset if inprespa[3:0] = 'b1111. figure 7. input port a reset structure 0 1 mux 2 3 1 0 vss pa[3] pa[3] vdd bit [0] bit [1] bit [2] bit [3] inprespa inprespa[3] inpres2pa[3] inpres1pa[3] input porta reset bit[2] selection input porta reset bit[1] selection input porta reset bit[0] selection input porta reset bit[3] selection input reset from porta
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 10 www.emmicroelectronic.com 4.3 digital watchdog timer reset the digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of ck1]. it will generate a system reset if it is not periodically cleared. the watchdog timer function can be inhibited by activating an inhibit digital watchdog bit ( nologicwd ) located in regvldcntl . at power up, and after any system reset, the watchdog timer is activated. if for any reason the cpu stops, then the watchdog timer can detect this situation and activate the system reset signal. this function can be used to detect program overrun, endless loops, etc. for normal operation, the watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 khz), or a system reset signal is generated. the watchdog timer is reset by writing a ?1? to the wdreset bit in the timer. this resets the timer to zero and timer operation restarts immediately. when a ?0? is written to wdreset there is no effect. the watchdog timer operates also in the standby mode and thus, to avoid a system reset, standby should not be active for more than 2.5 seconds. from a system reset state, the watchdog timer will become active after 3.5 seconds. however, if the watchdog timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. it is therefore recommended to use the prescaler irqhz1 interrupt to periodically reset the watchdog every second. it is possible to read the current status of the watchdog timer in regsyscntl2 . after watchdog reset, the counting sequence is (on each rising edge of ck[1]) : ?00?, ?01?, ?10?, ?11?, {wdval1 wdval0}. when reaching the ?11? state, the watchdog reset will be active within ? second. the watchdog reset activates the system reset which in turn resets the watchdog. if the watchdog is inhibited it?s timer is reset and therefore always reads ?0?. table 4.3.1 watchdog timer register regsyscntl2 bit name reset r/w description 3 wdreset 0 r/w reset the watchdog 1 -> resets the logic watchdog 0 -> no action the read value is always '0' 2 sleepen 0 r/w see operating modes (sleep) 1 wdval1 0 r watchdog timer data 1/4 ck[1] 0 wdval0 0 r watchdog timer data 1/2 ck[1] 4.4 cpu state after reset reset initializes the cpu as shown in table 4.4.1 below. table 4.4.1 initial cpu value after reset. name bits symbol initial value program counter 0 12 pc0 $000 (as a result of jump 0) program counter 1 12 pc1 undefined program counter 2 12 pc2 undefined stack pointer 2 sp sp[0] selected index register 7 ix undefined carry flag 1 cy undefined zero flag 1 z undefined halt 1 halt 0 instruction register 16 ir jump 0 periphery registers 4 reg..... see peripheral memory map
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 11 www.emmicroelectronic.com 5. oscillator and prescaler 5.1 oscillator a built-in crystal oscillator generates the system operating clock for the cpu and peripheral blocks, from an externally connected crystal (typically 32.768khz). the oscillator circuit is supplied by the regulated voltage, vreg. in sleep mode the oscillator is stopped. em?s special design techniques guarantee the low current consumption of this oscillator. the external impedance between the oscillator pads must be greater than 10 mohm. connection of any other components to the two oscillator pads must be confirmed by em microelectronic-marin sa. 5.2 prescaler the prescaler consists of fifteen elements divider chain which delivers clock signals for the peripheral circuits such as timer/counter, buzzer, lcd voltage multiplier, debouncer and edge detectors, as well as generating prescaler interrupts. the input to the prescaler is the system clock signal. power on initializes the prescaler to hex(0001). table 5.2.1 prescaler clock name definition function name 32 khz xtal function name 32 khz xtal system clock ck[16] 32768 hz system clock / 256 ck[8] 128 hz system clock / 2 ck[15] 16384 hz system clock / 512 ck[7] 64 hz system clock / 4 ck[14] 8192 hz system clock / 1024 ck[6] 32 hz system clock / 8 ck[13] 4096 hz system clock / 2048 ck[5] 16 hz system clock/ 16 ck[12] 2048 hz system clock / 4096 ck[4] 8 hz system clock / 32 ck[11] 1024 hz system clock / 8192 ck[3] 4 hz system clock / 64 ck[10] 512 hz system clock / 16384 ck[2] 2 hz system clock / 128 ck [9] 256 hz system clock / 32768 ck[1] 1 hz table 5.2.2 control of prescaler register regpresc bit name reset r/w description 3 pwmon 0 r/w see 10 bit counter 2 respresc 0 r/w write reset prescaler 1 -> resets the divider chain from ck[14] down to ck[2], sets ck[1]. 0 -> no action. the read value is always '0' 1 printsel 0 r/w interrupt select. 0 -> interrupt from ck[4] 1 -> interrupt from ck[6] 0 debsel 0 r/w debouncer clock select. 0 -> debouncer with ck[8] 1 -> debouncer with ck[11] or ck[14] with debsel = 1 one may choose either the ck[11] or ck[14] debouncer frequency by selecting the corresponding metal mask option. relative to 32khz the corresponding max. debouncer times are then 2 ms or 0.25 ms. for the metal mask selection refer to chapter 16.1.5. switching the printsel may generate an interrupt request. avoid it with maskirq32/8 = 0 selection during the switching operation. figure 8. prescaler frequency timing system clock ck[16] ck[15] ck[14] horizontal scale change ck[2] ck[1] first positive edge of 1 hz clock is 1s after the falling reset edge prescaler reset
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 12 www.emmicroelectronic.com the prescaler contains 3 interrupt sources: - irq32/8 ; this is ck[6] or ck[4] positive edge interrupt, the selection is depending on bit printsel. - irqhz1 ; this is ck[1] positive edge interrupt - irqblink ; this is 3/4 of ck[1] period interrupt there is no interrupt generation on reset. the first irqhz1 interrupt occurs 1 sec (32khz) after reset. a possible application for the irqblink is lcd-display blinking control together with irqhz1. figure 9. prescaler interrupts ck[2] irqblink irq hz1 ck[1]
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 13 www.emmicroelectronic.com 6. input and output ports the em6620 has: - one 4-bit input port ( port a ) - one 4-bit input/output port. ( port b ) pull-up and pull-down resistors can be added to all this ports with metal and/or register options. 6.1 ports overview table 6.1.1 input and output ports overview port mode mask(m:) or register(r:) option function bitwise multi-function on ports pa [3:0] input m: pull-up m: pull-down (default) r: pull(up/down) select r: debounced or direct input for irq request and counter r: + or - for irq-edge and counter r: input reset combination -input -bit-wise interrupt request -software test variable conditional jump -pa[3],pa[0] input for the event counter -pa[3] input for the millisecond counter -port a reset inputs pa[3] 10 bit event counter clock start / stop of msc pa[2] - - pa[1] - - pa[0] 10 bit event counter clock - pb [3:0] bit-wise input or output r: cmos or nch open drain output r: pull-down on input r: pull-up on input -input or output -pb[3] for the pwm output -pb[2:0] for the ck[16,12,1] output -tristate output - pb[0] dynamic input comparator pb[3] pwm output pb[2] ck[1] output pb[1] ck[12] output pb[0] ck[16] output comp. input
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 14 www.emmicroelectronic.com 6.2 port a the em6620 has one four bit general purpose cmos input port. the port a input can be read at any time, pull- up or pull-down resistors can be chosen. all selections concerning port a are bit-wise executable. i.e. pull-up on pa[2], pull-down on pa[0], positive irq edge on pa[0] but negative on pa[1], etc. in sleep mode the port a inputs are continuously monitored to match the input reset condition which will immediately wake up the em6620. the pull-up or pull-down resistors remain active as defined in the option register. figure 10. input port a configuration intedgpa[n]=0 nodebintpa[n]=1 mask opt mpapu[n] pa3 for the millisecond counter irqpa[3:0] pa[n]terminal pa0, pa3 for 10-bit counter mask opt mpapd[n] debouncer p testvar ck[8] ck[11] or ck[14] db[3:0] nopull[n] vbat (vdd ) vss 6.2.1 irq on port a for interrupt request generation (irq) one can choose direct or debounced input and positive or negative edge irq triggering. with the debouncer selected ( optdebintpa ) the input must be stable for two rising edges of the selected debouncer clock ( regpresc ). this means a worst case of 16ms(default) or 2ms (0.25ms by metal mask) with a system clock of 32khz. either a positive or a negative edge on the port a inputs - after debouncer or not - can generate an interrupt request. this selection is done in the option register optintedgpa. all four bits of port a can provide an irq, each pin with its own interrupt mask bit in the regirqmask1 register. when an irq occurs, inspection of the regirq1 , regirq2 and regirq3 registers allow the interrupt to be identified and treated. at power on or after any reset the regirqmask1 is set to 0, thus disabling any input interrupt. a new interrupt is only stored with the next active edge after the corresponding interrupt mask is cleared. see also the interrupt chapter 9. it is recommended to mask the port a irq?s while one changes the selected irq edge. else one may generate a irq (software irq). i.e. pa[0] on ?0? then changing from positive to negative edge selection on pa[0] will immediately trigger an irqpa[0] if the irq was not masked.
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 15 www.emmicroelectronic.com 6.2.2 pull-up/down each of the input port terminals pa[3:0] has a resistor integrated which can be used either as pull-up or pull- down resistor, depending on the selected metal mask options. the pull resistor can be inhibited using the nopullpa[n] bits in the register optnopullpa. refer also to chapter 16.1.1 . table 6.2.1. pull-up or pull-down resistor on port a select option mask pull-up mpapu[n] option mask pull-down mpapd[n] nopullpa[n] value action no no x no pull-up, no pull-down no yes 0 no pull-up, pull-down no yes 1 no pull-up, no pull-down yes no 0 pull-up, no pull-down yes no 1 no pull-up , no pull-down yes yes x not allowed* * only pull-up or pull-down may be chosen on any port a terminal (one choice is excluding the other) any port a input must never be left open (high impedance state, not connected, etc. ) unless the internal pull resistor is in place (mask option) and switched on (register selection). any open input may draw a significant cross current which adds to the total chip consumption. 6.2.3 software test variables the port a terminals pa[2:0] are also used as input conditions for conditional software branches. independent of the optdebintpa and the optintedgpa. these cpu inputs are always debounced and non-inverted. - debounced pa[0] is connected to cpu testvar1 - debounced pa[1] is connected to cpu testvar2 - debounced pa[2] is connected to cpu testvar3 6.2.4 port a for 10-bit counter and msc the pa[0] and pa[3] inputs can be used as the clock input terminal for the 10 bit counter in "event count" mode. as for the irq generation one can choose debouncer or direct input with the register optdebintpa and non- inverted or inverted input with the register optintedgpa . debouncer input is always recommended. pad input pa[3] is also used as start/stop control for the millisecond counter. this control signal is derived from pa[3], it is independent of the port a debouncer and edge selection. refer also to figure 10. 6.3 port a registers table 6.3.1 register regpa bit name reset r/w description 3 pa[3] - r* pa[3] input status 2 pa[2] - r* pa[2] input status 1 pa[1] - r* pa[1] input status 0 pa[0] - r* pa[0] input status * direct read on port a terminals with n=0?3
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 16 www.emmicroelectronic.com table 6.3.2 register regirqmask1 bit name reset r/w description 3 maskirqpa[3] 0 r/w interrupt mask for pa[3] input 2 maskirqpa[2] 0 r/w interrupt mask for pa[2] input 1 maskirqpa[1] 0 r/w interrupt mask for pa[1] input 0 maskirqpa[0] 0 r/w interrupt mask for pa[0] input default "0" is: interrupt request masked, no new request stored table 6.3.3 register regirq1 bit name reset r/w description 3 irqpa[3] 0 r/w* interrupt request on pa[3] 2 irqpa[2] 0 r/w* interrupt request on pa[2] 1 irqpa[1] 0 r/w* interrupt request on pa[1] 0 irqpa[0] 0 r/w* interrupt request on pa[0] w*; write "1" clears the bit, write "0" has no action, default "0" is: no interrupt request table 6.3.4 register optintedgpa bit name power on value r/w description 3 intedgpa[3] 0 r/w interrupt edge select for pa[3] 2 intedgpa[2] 0 r/w interrupt edge select for pa[2] 1 intedgpa[1] 0 r/w interrupt edge select for pa[1] 0 intedgpa[0] 0 r/w interrupt edge select for pa[0] default "0" is: positive edge selection table 6.3.5 register optdebintpa bit name power on value r/w description 3 nodebintpa[3] 0 r/w interrupt debounced for pa[3] 2 nodebintpa[2] 0 r/w interrupt debounced for pa[2] 1 nodebintpa[1] 0 r/w interrupt debounced for pa[1] 0 nodebintpa[0] 0 r/w interrupt debounced for pa[0] default "0" is: debounced inputs for interrupt generation table 6.3. register optnopullpa bit name power on value r/w description 3 nopullpa[3] 0 r/w pull-up/down selection on pa[3] 2 nopullpa[2] 0 r/w pull-up/down selection on pa[2] 1 nopullpa[1] 0 r/w pull-up/down selection on pa[1] 0 nopullpa[0] 0 r/w pull-up/down selection on pa[0] default "0" is depending on mask selection.
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 17 www.emmicroelectronic.com 6.4 port b the em6620 has one four bit general purpose i/o port. each bit can be configured individually by software for input/output, pull-up, pull-down and cmos or nch. open drain output type. the port outputs either data, frequency or pwm signals. 6.4.1 input / output mode each port b terminal is bit-wise bi-directional. the input or output mode on each port b terminal is set by writing the corresponding bit in the regpbcntl control register. to set for input (default), 0 is written to the corresponding bit of the regpbcntl register which results in a high impedance state for the output driver. the output mode is set by writing 1 in the control register, and consequently the output terminal follows the status of the bits in the regpbdata register. the port b terminal status can be read on address regpbdata even in output mode. be aware that the data read on port b is not necessary of the same value as the data stored on regpbdata register. see also figure 11 for details. while the dynamic input comparator is selected ( pb0compsel =?1?) the ppb[0] input is cut off, a read on port b ppb[0] returns ?1?. figure 11. port b architecture irqpb0comp pb0compresult port b direction reg portb data reg internal data bus mux a ctive pull-down i / o terminal pb[n] ddr[n] dr[n] db [ n ] rd pb0compselect for pb[0] rd for pb[3:1] multiplexed output multiplexed output active multiplexed outputs are: pwm, ck[16], ck[11], ck[1] port b control active pull-up if open drain mode sleep pd[n] pull-down option register od[n] open drain option register mask option mpbpd[n] pb0compenable mask option mpbpd[n] dynamic input comparator 1 4
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 18 www.emmicroelectronic.com 6.4.2 pull-up/down for each terminal of pb[3:0] an internal input pull-up (metal mask mpbpu[n]) or pull-down (metal mask mpbpd[n]) resistor can be connected per metal mask option. per default the two resistors are in place. in this case one can chose per software to have either a pull-up, a pull-down or no resistor. see below. for metal mask selection and available resistor values refer to chapter 16.1.2. pull-down on : mpbpd[n] must be in place , and the bit nopdpb [n] must be ?0? . pull-down off : mpbpd[n] is not in place, or if mpbpd[n] is in place nopdpb [n] = ?1? cuts off the pull-down. or selecting nchopdpb [n] = ?1? cuts off the pull-down. pull-up on * : mpbpu[n] must be in place, and the bit nchopdpb [n] must be ?1? , and the bit pbiocntl[n] = ?0? (input mode) or if pbiocntl[n] = ?1? while pbdata [n] = 1. pull-up off* : mpbpu[n] is not in place, or if mpbpu[n] is in place nchopdpb [n] = ?0? cuts off the pull-up, or if mpbpu[n] is in place and if nchopdpb [n] = ?1? then pbdata[n] = 0 cuts off the pull-up. never can pull-up and pull-down be active at the same time. for power saving one can switch off the port b pull resistors between two read phases. no cross current flows in the input amplifier while the port b is not read. the recommended order is : ? switch on the pull resistor. ? allow sufficient time - rc constant - for the pull resistor to drive the line to either v ss or v dd . ? read the port b ? switch off the pull resistor minimum time with current on the pull resistor is 4 periods of the system clock, if the rc constant is lower than 1 system clock period. adding a nop before reading moves the number of periods with current in the pull resistor to 6 and the maximum rc delay to 3 clock periods. 6.4.3 cmos / nch. open drain output the port b outputs can be configured as either cmos or nch. open drain outputs. in cmos both logic ?1? and ?0? are driven out on the terminal. in nch. open drain only the logic ?0? is driven out on the terminal, the logic ?1? value is defined by the internal pull-up resistor (if implemented) or high impedance. if using the dynamic input comparator one must put the pb[0] in cmos input mode and should not use any pull resistor on this terminal. if not doing so the device may draw excessive current. figure 12. cmos or open drain outputs i / o term inal pb[n] mux active pullup for high state dr[n] frequency outputs tri-state output buffer : high im pedance for data = 1 i / o term inal pb[n] mux dr[n] frequency outputs tri-state output buffer : closed data 1 cmos output nch. open drain output
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 19 www.emmicroelectronic.com 6.4.4 pwm and frequency output pb[3] can also be used to output the pwm (pulse width modulation) signal from the 10-bit counter, the ck[16], ck[11] as well as the ck[1] prescaler frequencies. -selecting ck[16] output on pb[0] with bit pb32khzout in register optselpb -selecting ck[11] output on pb[1] with bit pb2khzout in register optselpb -selecting ck[1 ] output on pb[2] with bit pb1hzout in register optselpb -selecting pwm output on pb[3] with bit pwmon in register regpresc. 6.5 pb[0] dynamic input comparator the em6620 has one dynamic input comparator on pb[0], such that pb[0] input voltage level is compared at regular intervals (ck[12] clock period) with the svld detection level (default : 2.0v). to select this function, the bit pb0compselect in register regpb0comp must be set to ?1. if using the dynamic input comparator one must put the pb[0] in cmos input mode and should not use any pull resistor on this terminal. the comparator shares the same internal block as the svld function, so one can only use one or the other function at the same time. with bit pb0compselect set to ?1? the comparator is chosen, ?0? selects the svld. setting the bit pb0compenable to ?1? enables the measurements. the worst case first measurement time is : ck[9] clock period + ck[14] clock period (synchronization + effective measurement) (32khz -> 4.125ms) the time between two consecutive effective measurements is equal to 3 ck[14] clock periods. the measurement stops at the end of the next measurement cycle after pb0compenable is cleared. at the end of each measurement, the result is stored in pb0compresult bit. at any time during the measurement pb0compresult bit can be read : if the result is - ?0?, the input level is greater than the detection level - ?1?, the input level is lower than the detection level. an interrupt request irqpb0comp is generated on each result change except after the first measurement. this interrupt request can be masked (default) ( maskirqpb0comp bit). see section 9 for more information about the interrupt handling. see also section supply voltage level detector on page 33.
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 20 www.emmicroelectronic.com 6.6 port b registers table 6.6.1 register regpbdata bit name reset r/w description 3 pbdata[3] - r* /w pb[3] input and output 2 pbdata[2] - r* /w pb[2] input and output 1 pbdata[1] - r* /w pb[1] input and output 0 pbdata[0] - r* /w pb[0] input and output r* : direct read on port b terminal (not the internal register read). table 6.6.2 register regpbcntl bit name reset r/w description 3 pbiocntl[3] 0 r/w i/o control for pb[3] 2 pbiocntl[2] 0 r/w i/o control for pb[2] 1 pbiocntl[1] 0 r/w i/o control for pb[1] 0 pbiocntl[0] 0 r/w i/o control for pb[0] default "0" is: portb in input mode table 6.6.3 register regpb0comp bit name reset r/w description 3------ 2 pb0compresult 0 r comparator result flag 1 pb0compenable 0 r/w comparator measurements enable 0 pb0compselect 0 r/w dynamic input comparator function default "0" is: power supply voltage level detection table 6.6.4 register optfselpb bit name power on value r/w description 3 pb1hzout 0 r/w ck[1] output on pb[2] 2 pb2khzout 0 r/w ck[12] output on pb[1] 1 pb32khzout 0 r/w ck[16] output on pb[0] 0 noinputres 0 r/w no input reset from port a default "0" is: no frequency output, port a can reset the em6620. table 6.6.5 option register optnopdpb bit name power on value r/w description 3 nopdpb[3] 0 r/w no pull-down on pb[3] 2 nopdpb[2] 0 r/w no pull-down on pb[2] 1 nopdpb[1] 0 r/w no pull-down on pb[1] 0 nopdpb[0] 0 r/w no pull-down on pb[0] default "0" is: pull-down on table 6.6.6 option register optnchopdpb bit name power on value r/w description 3 nchopdpb[3] 0 r/w nch. open drain on pb[3] 2 nchopdpb[2] 0 r/w nch. open drain on pb[2] 1 nchopdpb[1] 0 r/w nch. open drain on pb[1] 0 nchopdpb[0] 0 r/w nch. open drain on pb[0] default "0" is: cmos on pb[3..0]
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 21 www.emmicroelectronic.com 7. 10-bit counter the em6620 has a built-in universal cyclic counter. it can be configured as 10, 8, 6 or 4-bit counter. if 10-bits are selected we call that full bit counting, if 8, 6 or 4-bits are selected we call that limited bit counting. the counter works in up- or down count mode. eight clocks can be used as the input clock source, six of them are prescaler frequencies and two are coming from the input pads pa[0] and pa[3]. in this case the counter can be used as an event counter. the counter generates an interrupt request irqcount0 every time it reaches 0 in down count mode or 3ff in up count mode. another interrupt request irqcntcomp is generated in compare mode whenever the counter value matches the compare data register value. each of this interrupt requests can be masked (default). see section 9 for more information about the interrupt handling. a 10-bit data register creg[9:0] is used to initialize the counter at a specific value (load into count[9:0] ). this data register ( creg[9:0] ) is also used to compare its value against count[9:0] for equivalence. a pulse-width-modulation signal (pwm) can be generated and output on port b terminal pb[3]. 7.1 full and limited bit counting in full bit counting mode the counter uses its maximum of 10-bits length (default ). with the bitsel[1,0] bits in register regcdatah one can lower the counter length, for irq generation, to 8, 6 or 4 bits. this means that actually the counter always uses all the 10-bits, but irqcount0 generation is only performed on the number of selected bits. the unused counter bits may or may not be taken into account for the irqcomp generation depending on bit selintfull . refer to chapter 7.4. figure 13. 10-bit counter block diagram en comparator ck up/down up/down counter en evcount counter read register regcdatal, m, h (count[9:0]) regcdatal, m, h (creg[9:0]) load irqcntcomp pwm irqcount0 data register db[3:0] pa[0] ck[15] ck[12] ck[10] ck[8] ck[4] ck[1] pa[3] ck mux regccntl1, 2 countfsel2 ...0 up/down start evcount load encomp table 6.6.1. counter length selection bitsel[1] bitsel[0 ] counter length 0 0 10-bit 018-bit 106-bit 114-bit
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 22 www.emmicroelectronic.com 7.2 frequency select and up/down counting 8 different input clocks can be selected to drive the counter. the selection is done with bits countfsel2?0 in register regccntl1 . 6 of this input clocks are coming from the prescaler. the maximum prescaler clock frequency for the counter is half the system clock and the lowest is 1hz. therefore a complete counter roll over can take as much as 17.07 minutes (1hz clock, 10 bit length) or as little as 977 s (ck[15], 4 bit length). the irqcount0 , generated at each roll over, can be used for time bases, measurements length definitions, input polling, wake up from halt mode, etc. the irqcount0 and irqcomp are generated with the system clock ck[16] rising edge. irqcount0 condition in up count mode is : reaching 3ff if 10-bit counter length (or ff, 3f, f in 8, 6, 4-bit counter length). in down count mode the condition is reaching ?0?. the non-selected bits are ?don?t care?. for irqcomp refer to section 7.4. note: the prescaler and the microprocessor clock?s are usually non-synchronous, therefore time bases generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down mode). however the prescaler clock can be synchronized with p commands using for instance the prescaler reset function. the two remaining clock sources are coming from the pa[0] or pa[3] terminals. refer to the figure 10 on page 14 for details. both sources can be either debounced (ck[11] or ck[8]) or direct inputs, the input polarity can also be chosen. the output after the debouncer polarity selector is named pa3 , pa0 respectively. for the debouncer and input polarity selection refer to chapter 6.2. in the case of port a input clock without debouncer, the counting clock frequency will be half the input clock on port a. the counter advances on every odd numbered port a negative edge ( divided clock is high level ). irqcount0 and irqcomp will be generated on the rising pa3 or pa0 input clock edge. in this condition the em6621 is able to count with a higher clock rate as the internal system clock (hi-frequency input). maximum port a input frequency is limited to 200khz (@v dd 1.5 v). if higher frequencies are needed, please contact em-marin. in both, up or down count (default) mode, the counter is cyclic. the counting direction is chosen in register regccntl1 bit up/down (default ?0? is down count). the counter increases or decreases its value with each positive clock edge of the selected input clock source. start up synchronization is necessary because one can not always know the clock status when enabling the counter. with evcount=0, the counter will only start on the next positive clock edge after a previously latched negative edge, while the start bit was already set to ?1?. this synchronization is done differently if event count mode (bit evcount ) is chosen. refer also to figure 15. internal clock synchronization. figure 14. counter clock timing prescaler frequencies or debounced port a clocks non-debounced port a clocks (system clock independent) system clock prescaler clock counting counter irq?s divided clock system clock port a clock counting c ounter ir q ?s
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 23 www.emmicroelectronic.com 7.3 event counting the counter can be used in a special event count mode where a certain number of events (clocks) on the pa[0] or pa[3] input are counted. in this mode the counting will start directly on the next active clock edge on the selected port a input. the event count mode is switched on by setting bit evcount in the register regccntl2 to ?1?.pa[3] and pa[0] inputs can be inverted depending on register optintedgpa and should be debounced. the debouncer is switched on in register optdebintpa bits nodebintpa[3,0]=0. its frequency depends on the bit debsel from register regpresc setting. the inversion of the internal clock signal derived from pa[3] or pa[0] is active with intedgpa[3] respectively intedgpa[0] equal to 1. refer also to figure 10 for internal clock signal generation. 7.4 compare function a previously loaded register value ( creg[9:0] ) can be compared against the actual counter value ( count[9:0] ) . if the two are matching (equality) then an interrupt ( irqcomp ) is generated. the compare function is switched on with the bit encomp in the register regccntl2 . with encomp = 0 no irqcomp is generated. starting the counter with the same value as the compare register is possible, no irq is generated on start. full or limited bit compare are possible, defined by bit selintfull in register regsyscntl1 . encomp must be written after a load operation ( load = 1). every load operation resets the bit encomp. full bit compare function. bit selintfull is set to ?1?. the function behaves as described above independent of the selected counter length. limited bit counting together with full bit compare can be used to generate a certain amount of irqcount0 interrupts until the counter generates the irqcomp interrupt. with pwmon =?1? the counter would have automatically stopped after the irqcomp, with pwmon =?0? it will continue until the software stops it. encomp must be cleared before setting selintfull and before starting the counter again. be careful, pwmon also redefines the port b pb[3] output data.(refer to section 7.5). limited bit compare with the bit selintfull set to ?0? (default) the compare function will only take as many bits into account as defined by the counter length selection bitsel[1:0] (see chapter 7.1). 7.5 pulse width modulation (pwm) the pwm generator uses the behavior of the compare function (see above) so encomp must be set to activate the pwm function.. at each roll over or compare match the pwm state - which is output on port b pb[3] - will toggle. the start value on pb[3] is forced while encomp is 0 the value is depending on the up or down count mode. every counter value load operation resets the bit encomp and therefore the pwm start value is reinstalled. setting pwmon to ?1? in register regpresc routes the counter pwm output to port b terminal pb[3]. insure that pb[3] is set to output mode . refer to section 6.4 for the port b setup. the pwm signal generation is independent of the limited or full bit compare selection bit selintfull. however if selintfull = 1 (full) and the counter compare function is limited to lower than 10 bits one can generate a predefined number of output pulses. in this case, the number of output pulses is defined by the value of the unused counter bits. it will count from the start value until the irqcomp match. one must not use a compare value of hex 0 in up count mode nor a value of hex 3ff (or ff,3f, f if limited bit compare) in down count mode. figure 15. internal clock synchronization ck start count[9:0 ] + / - 1 + / - 1 evcount = 0 ck start evcount = 0 ck start evcount = 1 ck start evcount = 1 count[9:0 ] + / - 1 count[9:0 ] count[9:0 ]
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 24 www.emmicroelectronic.com for instance, loading the counter in up count mode with hex 000 and the comparator with hex c52 which will be identified as : - bits[11:10] are limiting the counter to limits to 4 bits length, =03 (bitsel[1,0]) - bits [9:4] are the unused counter bits = hex 05 (bin 000101), (number of pwm pulses) - bits [3:0] (comparator value = 2). (length of pwm pulse) thus after 5 pwm-pulses of 2 clocks cycles length the counter generates an irqcomp and stops. the same example with selintfull=0 (limited bit compare) will produce an unlimited number of pwm at a length of 2 clock cycles. 7.5.1 how the pwm generator works. for up count mode ; setting the counter in up count and pwm mode the pb[3] pwm output is defined to be 0 ( encomp =0 forces the pwm output to 0 in upcount mode, 1 in downcount). each roll over will set the output to ?1? and each compare match will set it back to ?0?. the compare match for pwm always only works on the defined counter length. this, independent of the selintfull setting which is valid only for the irq generation. refer also to the compare setup in chapter 7.4. in above example the pwm starts counting up on hex 0, 2 cycles later compare match -> pwm to ?0?, 14 cycles later roll over -> pwm to ?1? 2 cycles later compare match -> pwm to ?0? , etc. until the completion of the 5 pulses. the normal irq generation remains on during pwm output. if no irq?s are wanted, the corresponding masks need to be set. in down count mode everything is inverted. the pwm output starts with the ?1? value. each roll over will set the output to ?0? and each compare match will set it back to ?1?. for limited pulse generation one must load the complementary pulse number value. i.e. for 5 pulses counting on 4 bits load bits[9 :4] with hex 3a (bin 111010). 7.5.2 pwm characteristics pwm resolution is : 10bits (1024 steps), 8bits (256 steps), 6bits (64 steps) or 4 bits (16 steps) the minimal signal period is : 16 (4-bit) x fmax* -> 16 x 1/ck[15] -> 977 s (32 khz) the maximum signal period is : 1024 x fmin* -> 1024 x 1/ck[1] -> 1024 s (32 khz) the minimal pulse width is : 1 bit -> 1 x 1/ck[15] -> 61 s (32 khz) * this values are for fmax or fmin derived from the internal system clock (32khz). much shorter (and longer) pwm pulses can be achieved by using the port a as frequency input. one must not use a compare value of hex 0 in up count mode nor a value of hex 3ff (or ff,3f, f if limited bit compare) in downcount mode. figure 16. pwm output in up count mode data+2 data+1 data-1 data ... 001 000 03f 03e pwm output irqcomp irqcount0 compare roll-over count[9 :0] clock figure 17. pwm output in down count mode data-2 data-1 data+1 data ... 3f e 3ff 000 001 pwm output irqcomp irqcount0 compare roll-over count[9 :0] clock
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 25 www.emmicroelectronic.com 7.6 counter setup regcdatal[3:0], regcdatam[3:0], regcdatah[1:0] are used to store the initial count value called creg[9:0] which is written into the count register bits count[9:0] when writing the bit load to ?1? in regccntl2 . this bit is automatically reset thereafter. the counter value count[9:0] can be read out at any time, except when using non-debounced high frequency port a input clock. to maintain data integrity the lower nibble count[3:0] must always be read first. the shcount[9:4] values are shadow registers to the counter. to keep the data integrity during a counter read operation (3 reads), the counter values [9:4] are copied into these registers with the read of the count[3:0] register. if using non-debounced high frequency port a input the counter must be stopped while reading the count[3:0] value to maintain the data integrity. in down count mode an interrupt request irqcount0 is generated when the counter reaches 0. in up count mode, an interrupt request is generated when the counter reaches 3ff (or ff,3f,f if limited bit counting). never an interrupt request is generated by loading a value into the counter register. when the counter is programmed from up into down mode or vice versa, the counter value count[9:0] gets inverted. as a consequence, the initial value of the counter must be programmed after the up/down selection. loading the counter with hex 000 is equivalent to writing stop mode, the start bit is reset, no interrupt request is generated. how to use the counter; if pwm output is required one has to put the port b[3] in output mode and set pwmon=1 in step 5. 1st, set the counter into stop mode ( start =0). 2nd, select the frequency and up- or down count mode in regccntl1. 3rd, write the data registers regcdatal, regcdatam, regcdatah (counter start value and length) 4th, load the counter, load =1, and choose the mode. ( evcount , encomp =0) 5th, select bits pwmon in regpresc and selintfull in regsyscntl1 6th, if compare mode desired , then write regcdatal, regcdatam, regcdatah (compare value) 7th, set bit start and select encomp in regccntl2 7.7 10-bit counter registers table 7.7.1 register regccntl1 bit name reset r/w description 3 up/down 0 r/w up or down counting 2 countfsel2 0 r/w input clock selection 1 countfsel1 0 r/w input clock selection 0 countfsel0 0 r/w input clock selection default : pa0 ,selected as input clock, down counting table 7.7.2 counter input frequency selection with countfsel[2..0] countfsel2 countfsel1 countfsel0 clock source selection 0 0 0 port a pa[0] 0 0 1 prescaler ck[15] 0 1 0 prescaler ck[12] 0 1 1 prescaler ck[10] 1 0 0 prescaler ck[8] 1 0 1 prescaler ck[4] 1 1 0 prescaler ck[1] 1 1 1 port a pa[3]
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 26 www.emmicroelectronic.com table 7.7.3 register regccntl2 bit name reset r/w description 3 start 0 r/w start/stop control 2 evcount 0 r/w event counter enable 1 encomp 0 r/w enable comparator 0 load 0 r/w write: load counter register; read: always 0 default : stop, no event count, no comparator, no load table 7.7.4 register regsyscntl1 bit name reset r/w description 3 inten 0 r/w general interrupt enable 2 sleep 0 r/w sleep mode 1 selintfull 0 r/w compare interrupt select 0 chtmdis 0 r/w for em test only default : interrupt on limited bit compare table 7.7.5 register regcdatal, counter/compare low data nibble bit name reset r/w description 3 creg[3] 0 w counter data bit 3 2 creg[2] 0 w counter data bit 2 1 creg[1] 0 w counter data bit 1 0 creg[0] 0 w counter data bit 0 3 count[3] 0 r data register bit 3 2 count[2] 0 r data register bit 2 1 count[1] 0 r data register bit 1 0 count[0] 0 r data register bit 0 table 7.7.6 register regcdatam, counter/compare middle data nibble bit name reset r/w description 3 creg[7] 0 w counter data bit 7 2 creg[6] 0 w counter data bit 6 1 creg[5] 0 w counter data bit 5 0 creg[4] 0 w counter data bit 4 3 shcount[7] 0 r data register bit 7 2 shcount[6] 0 r data register bit 6 1 shcount[5] 0 r data register bit 5 0 shcount[4] 0 r data register bit 4 table 7.7.7 register regcdatah, counter/compare high data nibble bit name reset r/w description 3 bitsel[1] 0 r/w bit select for limited bit count/compare 2 bitsel[0] 0 r/w bit select for limited bit count/compare 1 creg[9] 0 w counter data bit 9 0 creg[8] 0 w counter data bit 8 1 shcount[9] 0 r data register bit 9 0 shcount[8] 0 r data register bit 8 table 7.7.8 counter length selection bitsel[1] bitsel[0 ] counter length 0 0 10-bit 018-bit 106-bit 114-bit
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 27 www.emmicroelectronic.com 8. millisecond counter the em6620 has a built-in millisecond binary coded decimal counter. it can be used to measure the time elapsed between two events (hardware or software events). with a system clock of 32khz, the counter generates every 1/10 second or every second an interrupt request. the counter value read on registers regmscdatal , regmscdatam and regmscdatah is in binary coded decimal format (000 to 999). to maintain the data integrity for the 3 decimal digits inside bcd[11:0] one must stop the counter while reading the full 3 digit value. an overflow flag flsec is set whenever the counter reached 999. this flag is helpful when the counter is used in polling mode and twice the same value is read. in this case, if the flag is set to 1, it indicates that the two readings were 1 second apart, in the case the flag is not set, the two readings must have been very short one after the other. after every read of regmsccntl2 the flsec gets automatically reset. the millisecond counter is reset with every system reset. setting the resmsc flag located in register regmsccntl1 resets the counter value only. this flag is automatically reset after the write operation. for good resolution in pa3-mode use the ck[14 ] debouncer clock (250us). or if the 1/1000 sec is not relevant then choose ck[10] (4ms) as debouncer clock. doing so will save power. the debouncer selection is made in register regmsccntl2 bit debfreqsel. changing pa3edge while runen =1 or pa3/up =1 may generate a msc event (start or stop). this behavior is useful for the - cpu controlled start and pa3 controlled stop - mode, but in general one does all the setup before starting the counter. 8.1 pa[3] input for msc in hardware start/stop mode the counter is triggered with the port a terminal pa[3] input. in this case pa[3] is debounced with the prescaler ck[14] (or ck[10]) clock. the triggering edge selection is made with bit pa3edge in register regmsccntl2 (default negative edge). the pa[3] input for the millisecond counter is totally independent of the pa[3] interrupt edge selection and the pa[3] polarity selection for the 10 bit counter. however the pull-up or pull-down selection is common to all peripheries sharing the port a. 8.2 irq from msc an interrupt request irqmsc is send on either every 1/10 seconds or every second, depending on the bit intsel in register regmsccntl2 . for interrupt handling please refer to the interrupt control section. figure 18. msc block diagram bcd 1/10 sec regmsccntl1,2 pa3 debouncer en irqmsc runen pa3/up dt/msc data bus data data data intsel 1 sec 1/10 sec ck[10] ck[14 pa[3] terminal pa3internal ne g ed g posed g 1 0 pa3edge 0 1 0 1 4 ck1000 flsecl debfreqsel start/stop control dt/msc bcd 1/1000 sec bcd 1/100 sec this signal used as reference in text description
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 28 www.emmicroelectronic.com 8.3 msc-modes the millisecond counter can have many different modes of operation. the most common are : - cpu controlled start and stop. - cpu controlled start and pa[3] controlled stop. - port a terminal pa[3] controlled start and stop mode. - pulse width measurement of port a terminal pa[3] input signals. all these different modes are controlled with the bits in the registers regmsccntl1 and regmsccntl2. the main bits are : - dt/msc ; pulse-width or start stop measure. this bit only has a action if pa[3] input is chosen. if pulse- width measure is selected, the counter starts with the first active edge on pa[3] and stops with the next inverse edge (sets runen = 0). if msc measure selected, the counter starts with the first active pa[3] edge, stops on the next, restarts on the following etc. it does not reset runen . - pa3/p ; direct port a terminal pa[3] or cpu (p) controlled start and stop function. if direct pa[3] controlled start stop mode is chosen the counter, once enabled by setting runen/stop = 1, starts counting on the first active edge seen on pa[3]. it stops counting depending on the dt/msc bit either on the next inverse edge or on the next active edge. if p is chosen, the counter starts and stops depending on bit runen/stop . - runen/stop ; in cpu mode this bit starts or stops the counter. in pa3 mode it enables the counter which will start with the next event on port a terminal pa[3]. if dt and pa3 mode, the runen gets reset with the second active pa[3] edge. - pa3edge ; this bit selects the active pa[3] edge which will trigger the dt/msc selected measurement mode. it has no effect if pa3/p =0. default 0 is negative edge. 8.4 mode selection before using, the msc counter needs to be reset by setting bit resmsc to ?1?. this bit is automatically reset thereafter. then select the irq frequency and the counting mode. now the runen can be set to ?1? . to display the counter value during run you may only want to read the msb (1/10 sec) digit ,driven by irq or with polling, and fully read the msc value only once the counter is stopped. the counter data registers are read only. any reset (system reset, por, watchdog) is setting the msc into stop mode and clears the counter registers. ? cpu controlled start and stop as soon as the cpu writes the start bit runen/stop =1 the counter starts up counting until the cpu clears the start bit. the bit pa3/up is ?0? for this mode. figure 19. cpu controlled start stop counting stop start counter runen/stop cpu write
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 29 www.emmicroelectronic.com ? cpu controlled start and pa[3] controlled stop. in this mode setting the bit runen =1 while pa3/up =0 while immediately start the counting action. afterwards one needs to prepare for the stop by pa[3]. therefore the pa[3] start condition must first be fulfilled. this is in dt mode a rising edge on the pa3internal signal (pa3internal, refer to figure 18). in msc mode the start condition is a positive pulse on pa3internal signal. the creation of this edge or pulse is done per software by manipulating the pa3edge selection. see figure 20 for details. afterwards one can change to pa3 controlled stop mode ( pa3/up =1) where the next positive edge on pa3internal will stop the counter. in dt mode the runen/stop bit will be cleared with the pa3 stop condition where as in msc mode msc mode the runen is not cleared. ? pulse-width measurement of pa[3] input signals. in this mode the bit dt/msc =1 and pa3/up =1. setting runen/stop=1 enables the operation. the first positive edge on pa3internal signal will start the counter, the following negative edge will stop the counter end set bit runen/stop to 0 . pa3internal signal is a copy of the pa[3] terminal status if pa3edge =1. with pa3edge =0 pa3internal has the inverted pa[3] value. see also figure 18 and figure 21. ? port a pa[3] controlled start and stop mode. in this mode the bit dt/msc =0 and pa3/up =1. setting runen/stop=1 enables the operation. the first positive edge on pa3internal signal will start the counter , the second edge will stop the counter, the third one will restart, etc, . pa3internal signal is a copy of the pa[3] terminal status if pa3edge =1. with pa3edge =0 pa3internal has the inverted pa[3] value. see also figure 18 and figure 21. figure 20. cpu controlled start pa[3] controlled stop counting set in itia l values stop start pa3 start p d t /m s c = 1 , s to p on pa [ 3 ] risin g ed g e cpu w rite pa3ed g e pa3/up r unen/stop p a 3 in te rn a l c ount pa [ 3 ] set in itia l values counting stop start pa3 start p d t /m s c = 1 , s to p on pa [ 3 ] f a llin g ed g e cpu w rite pa3ed g e pa3/up runen/stop pa3internal count pa [ 3 ] counting set in itia l values stop start pa3 start p d t /m s c = 0 , s to p on pa [ 3 ] risin g ed g e cpu w rite pa3ed g e pa3/up r unen/stop p a 3 in te rn a l c ount pa[3] counting set in itia l values stop start pa3 start p d t /m s c = 0 , s to p on pa [ 3 ] f a llin g ed g e cpu w rite pa3ed g e pa3/up runen/stop pa3internal count pa[3] figure 21. dt/msc behavior restart stop start stop start counter runen counting counting counting pa3 internal period measurement dt/msc=0, pa3/up=1 pulse-width measurement dt/msc, pa3/up=1 counter runen pa3 internal
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 30 www.emmicroelectronic.com 8.5 millisecond counter registers table 8.5.1 register regmsccntl1 bit name reset r/w description 3 runen/stop 0 r/w enable counter 2 pa3/p 0 r/w port a or cpu start stop control 1 dt/msc 0 r/w pulse-width measurement 0 resmsc 0 r/w reset if write of 1 read value is always 0 default: stop, cpu controlled. table 8.5.2 register regmsccntl2 bit name reset r/w description 3 debfreqsel 0 r/w debouncer frequency select 2 pa3edge 0 r/w pa[3] edge selection 1 intsel 0 r/w interrupt source selection 0 flsec 0 r seconds flag default: ck[14] is debouncer clock, negative edge, 1/10 sec interrupt requests table 8.5.3 register regmscdatal bit name reset r/w description 3 bcd[3] 0 r 1/1000 seconds bcd value 3 2 bcd[2] 0 r 1/1000 seconds bcd value 2 1 bcd[1] 0 r 1/1000 seconds bcd value 1 0 bcd[0] 0 r 1/1000 seconds bcd value 0 table 8.5.4 register regmscdatam bit name reset r/w description 3 bcd[7] 0 r 1/100 seconds bcd value 3 2 bcd[6] 0 r 1/100 seconds bcd value 2 1 bcd[5] 0 r 1/100 seconds bcd value 1 0 bcd[4] 0 r 1/100 seconds bcd value 0 table 8.5.5 register regmscdatah bit name reset r/w description 3 bcd[11] 0 r 1/10 seconds bcd value 3 2 bcd[10] 0 r 1/10 seconds bcd value 2 1 bcd[9] 0 r 1/10 seconds bcd value 1 0 bcd[8] 0 r 1/10 seconds bcd value 0
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 31 www.emmicroelectronic.com 9. interrupt controller the em6620 has 12 different interrupt request sources individually maskable. these are: external(5) - port a, pa[3] .. pa[0] inputs - compare pb[0] input internal(8) - prescaler ck[1], blink, 32hz/8hz - millisecond counter 1/10sec or 1sec - 10-bit counter count0, countcomp - svld end of measure the svld and the compare share the same interrupt line. to be able to send an interrupt to the cpu, at least one of the interrupt request flags must be set ( irqxx ) and the general interrupt enable bit inten located in the register regsyscntl1 must be set to 1. the interrupt request flags can only be set by a positive edge of irqxx with the corresponding mask register bit ( maskirqxx ) set to 1. at power on or after any reset all interrupt request mask registers are cleared and therefore do not allow any interrupt request to be stored. also the general interrupt enable inten is set to 0 (no irq to cpu) by reset. after each read operation on the interrupt request registers regirq1 , regirq2 or regirq3 the contents of the addressed register are reset. therefore one has to make a copy of the interrupt request register if there was more than one interrupt to treat. each interrupt request flag may also be reset individually by writing 1 into it (clrintbit). interrupt handling priority must be resolved through software by deciding which register and which flag inside the register need to be serviced first. since the cpu has only one interrupt subroutine and because the irqxx registers are cleared after reading, the cpu does not miss any interrupt request which comes during the interrupt service routine. if any occurs during this time a new interrupt will be generated as soon as the software comes out of the current interrupt subroutine. figure 22. interrupt controller block diagram interrupt request capture register 12 input-or read clrintbit reset general int en irq to p one of these blocks for each irq db db[n] irqxx write mask write
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 32 www.emmicroelectronic.com any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the interrupt request register. all interrupt requests are stored in their irqxx registers depending only on their corresponding mask setting and not on the general interrupt enable status. whenever the em6620 goes into halt mode the inten bit is automatically set to 1, thus allowing to resume from halt mode with an interrupt. 9.1 interrupt control registers table 9.1.1 register regirq1 bit name reset r/w description 3 irqpa[3] 0 r/w* port a pa[3] interrupt request 2 irqpa[2] 0 r/w* port a pa[2] interrupt request 1 irqpa[1] 0 r/w* port a pa[1] interrupt request 0 irqpa[0] 0 r/w* port a pa[0] interrupt request w*; writing of 1 clears the corresponding bit. table 9.1.2 register regirq2 bit name reset r/w description 3 irqhz1 0 r/w* prescaler interrupt request 2 irqhz32/8 0 r/w* prescaler interrupt request 1 irqblink 0 r/w* prescaler interrupt request 0 irqpb0comp 0 r/w* compare interrupt request w*; writing of 1 clears the corresponding bit. table 9.1.3 register regirq3 bit name reset r/w description 3 irqvld 0 r/w* vld interrupt request 2 irqmsc 0 r/w* millisecond counter int. request 1 irqcount0 0 r/w* counter interrupt request 0 irqcntcomp 0 r/w* counter interrupt request w*; writing of 1 clears the corresponding bit. table 9.1.4 register regirqmask1 bit name reset r/w description 3 maskirqpa[3] 0 r/w port a pa[3] interrupt mask 2 maskirqpa[2] 0 r/w port a pa[2] interrupt mask 1 maskirqpa[1] 0 r/w port a pa[1] interrupt mask 0 maskirqpa[0] 0 r/w port a pa[0] interrupt mask interrupt is not stored if the mask bit is 0. table 9.1.5 register regirqmask2 bit name reset r/w description 3 maskirqhz1 0 r/w prescaler interrupt mask 2 maskirqhz32/8 0 r/w prescaler interrupt mask 1 maskirqblink 0 r/w prescaler interrupt mask 0 maskirqpb0comp 0 r/w compare interrupt mask interrupt is not stored if the mask bit is 0. table 9.1.6 register regirqmask3 bit name reset r/w description 3 maskirqvld 0 r/w vld interrupt mask 2 maskirqmsc 0 r/w millisecond counter interrupt mask 1 maskirqcount0 0 r/w counter interrupt mask 0 maskirqcntcomp 0 r/w counter interrupt mask interrupt is not stored if the mask bit is 0
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 33 www.emmicroelectronic.com 10. supply voltage level detector the em6620 has a built-in supply voltage level detector (svld), such that the cpu can compare the supply voltage against a pre-selected value. during sleep mode this function is inhibited. the cpu activates the supply voltage level detector by writing vldstart =1 in the register regvldcntl . the actual measurement starts on the next ck[9] rising edge and lasts during the ck[9] high period (2ms at 32khz). the busy flag vldbusy stays high from start set until the measurement is finished. the worst case time until the result is available is 1.5 ck[9] prescaler clock periods (32khz -> 6ms). during the actual measurement the device will draw an additional 5ua of i vdd current. after the end of the measure an interrupt request irqvld is generated and the result is available by inspection of the bit vldresult . if the result is read 0, then the power supply voltage was greater than the detection level value. if read 1, the power supply voltage was lower than the detection level value. during each read while busy=1 the vldresult is not guaranteed. 10.1 svld register table 10.1.1 register regvldcntl bit name reset r/w description 3 vldresult 0 r* vld result flag 2 vldstart 0 w vld start 2 vldbusy 0 r vld busy flag 1 nooscwd 0 r/w no oscillator watchdog 0 nologicwd 0 r/w no logic watchdog r*; vldresult is not guaranteed while vldbusy=1 the svld and the pb0 input comparator are using the same internal measurement block. therefore only one of the two functions can be activated at the same time. figure 23. svld timing diagram vbat =vdd compare level ck[9] (256hz) cpu start s measure busy flag measure 1 0 result read result svld >vbat svld em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 34 www.emmicroelectronic.com 11. ram the em6620 has one 64x4 bit ram built-in located on addresses hex 0 to 3f. all the ram nibbles are direct addressable. ram extension : unused r/w registers can often be used as possible ram extension. be careful not to use registers which start, stop, or reset some functions. unused lcd register latches can also be used as ram extension. in case of 3 times multiplex and using all the 8 segment outputs you may have two additional 4 bit registers available. also for each unused segment output you may have one additional 4 bit register. figure 24. ram architecture ram1_63 ram1_62 ram1_61 ram1_60 ram1_0 4 bit r/w 4 bit r/w 4 bit r/w 4 bit r/w 4 bit r/w . . . . . . ram1_3 ram1_2 ram1_1 4 bit r/w 4 bit r/w 4 bit r/w 64 x 4 direct addressable ram1
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 35 www.emmicroelectronic.com 12. lcd driver the em6620 has a built-in liquid crystal display driver. a maximum of 32 segments can be displayed using the 8 segment driver outputs (seg[8:1) in 4:1 multiplex - 24 segments in the case of 3:1 multiplex - and the 4 back-planes (com[4:1]). the lcd driver has its own voltage regulator (1.05 volt) and voltage multiplier to generate the driver bias voltages vl1, vl2 and vl3 (vlcd). using the metal1 mask the user can choose higher lcd reference voltages. please check with em marin the possible values and their impact on power consumption. the special architecture of this lcd driver allows the user to specify the data and address for each individual segment by metal mask option. it therefore adapts to every possible lcd display with a maximum of 32 independent segments. the lcd clock frequency is 256hz. thus the frame frequency is 256/8 hz if 4:1 multiplex, or 256/6 if 3:1 multiplex. figure 25. lcd architecture reflcd lcd external supply lcd blank address bus seg[n] x3 enable x2 x1 voff lcd off von mux output switches voltage multiplier phase selection data latches data bus phase 1 to 4 3 4 2 1 vl1 vl2 vl3
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 36 www.emmicroelectronic.com 12.1 lcd control the lcd driver has two control registers reglcdcntl1,2 to optimize for display contrast, power consumption, operation mode and bias voltage source. lcdextsupply: choosing external supply (lcdextsupply=?1?) disables the internal lcd voltage regulator and voltage multiplier, it also puts the bias voltage terminals vl1, vl2 and vl3 into high impedance state. external bias levels can now be connected to the vl1, vl2 and vl3 terminals. (resistor divider chain or others). another way to adapt the vl1, vl2 and vl3 levels to specific user needs is to overdrive the vl1 output (lcdextsupply=0) with the desired value. the internal multiplier will multiply this new vl1 level to generate the corresponding levels vl2 and vl3. the bit lcdextsupply is only reset by initial por. lcd4mux: with this switch one selects either 3:1 or 4:1 (default) times multiplexing of the 8 segment driver outputs. in the case of 3:1 multiplexing the com[4] is off. lcdoff: disables the lcd. the voltage multiplier and regulator are switched off ( 0 current ).the segment latch information is maintained. the vl1, vl2 and vl3 outputs are pulled to v ss . lcdblank: all segment outputs are turned off. the voltage multiplier and regulator remain switched on. lcdblank can be used with the 1hz and blink interrupt to let the whole display blink (software controlled). cktripsel1,0: selecting the appropriate voltage multiplier frequency to optimize display contrast and power consumption. the value to use is also depending on the selected multiplier booster capacitors (typically 100nf). 12.2 lcd addressing the lcd driver addressing is direct using the registers lcd_0 , lcd_1 , lcd_2 until lcd_15 . all lcd segment registers are r/w.. a total of 16 addresses are available to the user to define the addressing of the lcd segment latches. for each of these latches the user may also choose the data bit to be connected. see also section 12.3. however only 8x4 lcd segment latches are implemented. the unused address and bit locations are empty and can not be used as ram. figure 26. lcd addressing 4 bit r/w lcd_10 lcd_9 4 bit r/w lcd_8 4 bit r/w lcd_7 4 bit r/w 4 bit r/w lcd_6 4 bit r/w lcd_5 lcd_4 4 bit r/w lcd_3 4 bit r/w lcd_2 4 bit r/w 4 bit r/w 4 bit r/w lcd_1 lcd_0 4 bit r/w lcd_15 lcd_14 4 bit r/w lcd_13 4 bit r/w lcd_12 4 bit r/w 4 bit r/w lcd_11 16 x 4 direct addressable lcd latches but maximum 8x4 bits are r/w
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 37 www.emmicroelectronic.com 12.3 free segment allocation each segment (seg[8:1]) terminal outputs the time multiplexed information from its 4 segment data latches. data latch 1 outputs during phase1, latch 2 during phase 2, latch 3 during phase 3 and latch 4 during phase 4. in the case of 3 to 1 multiplexing the phase 4 is not used. this phase information together with the common (com[4:1]), also called back-planes, outputs defines if a given segment is light or not. com[1] is on during phase 1 and off during phase 2,3,4 , com[2] is on during phase 2 and off during phase 1,3,4 , etc. for each segment data latch the address location within the lcd address spacing ( lcd_15 ... lcd_0 --> lcdadr[15:0] ) can be user defined. for each segment data latch the data bus connection (db[3:0]) can be user defined. segment outputs com[1] com[2] com[3] com[4] seg[1] db[0], lcdadr[0] db[1], lcdadr[0] db[2], lcdadr[0] db[3], lcdadr[0] seg[2] db[0], lcdadr[1] db[1], lcdadr[1] db[2], lcdadr[1] db[3], lcdadr[1] seg[3] db[0], lcdadr[2] db[1], lcdadr[2] db[2], lcdadr[2] db[3], lcdadr[2] ... ... ... ... ... seg[6] db[0], lcdadr[5] db[1], lcdadr[5] db[2], lcdadr[5] db[3], lcdadr[5] seg[7] db[0], lcdadr[6] db[1], lcdadr[6] db[2], lcdadr[6] db[3], lcdadr[6] seg[8] db[0], lcdadr[7] db[1], lcdadr[7] db[2], lcdadr[7] db[3], lcdadr[7] 12.4 lcd registers table 12.4.1 register reglcdcntl1 bit name reset r/w description 3-- 2-- 1 cktripsel1 0 r/w lcd multiplier clock select 0 cktripsel0 0 r/w lcd multiplier clock select table 12.4.2 multiplier clock frequency select cktripsel0 cktripsel1 multiplier clock on 32 khz operation 0 0 ck[10] 512 hz 1 0 ck[9] 256 hz 0 1 ck[8] 128 hz 1 1 ck[7] 64 hz table 12.4.3 register reglcdcntl2 bit name reset r/w description 3 lcdblank 1 r/w lcd segment outputs off 2 lcdoff 1 r/w lcd off (multiplier off) 1 lcd4mux 1 r/w 4 : 1 multiplexed 0 lcdextsupply x (0 on por) r/w external supply for vl1, vl2 and vl3 lcdextsupply is set to ?0? by por only
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 38 www.emmicroelectronic.com figure 27. lcd multiplexing waveform value = hex 8 seg[5] vl1 vl2 vl3 v ss com2 com1 vl1 vl2 vl3 v ss vl1 vl2 vl3 v ss frame cklcd com4 com3 vl1 vl2 vl3 v ss vl1 vl2 vl3 v ss seg[4] seg[3] vl1 vl2 vl3 v ss vl1 vl2 vl3 v ss value = hex 4 value = hex 2 seg[2] seg[1] vl1 vl2 vl3 v ss vl1 vl2 vl3 v ss value = hex 1 value = hex 0 com4 - seg[5] vl1 vl2 vl3 v ss value = hex 8 -vl2 -vl1 -vl3 com3 - seg[4] vl1 vl2 vl3 v ss value = hex 4 -vl2 -vl1 -vl3 com2 - seg[3 ] vl1 vl2 vl3 v ss value = hex 2 -vl2 -vl1 -vl3 com1 - seg[1 ] vl1 vl2 vl3 v ss value = hex 0 -vl2 -vl1 -vl3 com1 - seg[2 ] vl1 vl2 vl3 v ss value = hex 1 -vl2 -vl1 -vl3 seg[2] seg[1] com3 com4 seg[5] seg[4] seg[3] com1 com2
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 39 www.emmicroelectronic.com 13. peripheral memory map reset values are valid after power up or after every system reset. register name add hex add dec reset value read bits write bits remarks b'3210 read / write bits ram_0 00 0 xxxx 0: data0 1: data1 2: data2 3: data3 direct addressable ram 64x4 ... ... ... ... ... ram_63 3f 63 xxxx 0: data0 1: data1 2: data2 3: data3 direct addressable ram 64x4 lcd_0 40 64 xxxx 0: data0 1: data1 2: data2 3: data3 direct addressable lcd ... ... ... ... lcd_15 4f 79 xxxx 0: data0 1: data1 2: data2 3: data3 direct addressable lcd regpa 50 80 xxxx 0: pa[0] 1: pa[1] 2: pa[2] 3: pa[3] ---- read port a directly regpbcntl 51 81 0000 0: pbiocntl[0] 1: pbiocntl[1] 2: pbiocntl[2] 3: pbiocntl[3] port b control default: input mode regpbdata 52 82 xxxx 0: pb[0] 1: pb[1] 2: pb[2] 3: pb[3] 0: pbdata[0] 1: pbdata[1] 2: pbdata[2] 3: pbdata[3] port b data output pin port b read default : 0 regpb0comp 53 83 0000 0: pb0compselect 1: pb0compenable 2: pb0compresult 3: '0' 0: pb0compselect 1: pb0compenable 2: -- 3: -- port b[0] dynamic input comparator control regccntl1 5b 91 0000 0: countfsel0 1: countfsel1 2: countfsel2 3: up/down 10 bit counter control 1; frequency and up/down regccntl2 5c 92 0000 0: '0' 1: encomp 2: evcount 3: start 0 : load 1: encomp 2: evcount 3: start 10 bit counter control 2; comparison, event counter and start
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 40 www.emmicroelectronic.com register name add hex add dec reset value read bits write bits remarks b'3210 read / write bits regcdatal 5d 93 0000 0: count[0] 1: count[1] 2: count[2] 3: count[3] 0: creg[0] 1: creg[1] 2: creg[2] 3: creg[3] 10 bit counter data low bits regcdatam 5e 94 0000 0: count[4] 1: count[5] 2: count[6] 3: count[7] 0: creg[4] 1: creg[5] 2: creg[6] 3: creg[7] 10 bit counter data middle bits regcdatah 5f 95 0000 0: count[8] 1: count[9] 2: bitsel[0] 3: bitsel[1] 0: creg[8] 1: creg[9] 2: bitsel[0] 3: bitsel[1] 10 bit counter data high bits regmsccntl1 60 96 0000 0: '0' 1: dt/msc 2: pa3/p 3:runen/stop 0: resmsc 1: dt/msc 2: pa3/p 3:runen/stop millisecond counter control register 1; reset, delta time, control source regmsccntl2 61 97 0000 0: flsec 1: intsel 2: pa3edge 3: debfreqsel 0: -- 1: intsel 2: pa3edge 3: debfreqsel millisecond counter control register 2; 1 sec flag, interrupt and pa3 edge select regmscdatal 62 98 0000 0: bcd[0] 1: bcd[1] 2: bcd[2] 3: bcd[3] 0: - 1: - 2: - 3: - millisecond counter; binary coded decimal value, low nibble regmscdatam 63 99 0000 0: bcd[4] 1: bcd[5] 2: bcd[6] 3: bcd[7] 0: - 1: - 2: - 3: - millisecond counter; binary coded decimal value, middle nibble regmscdatah 64 100 0000 0: bcd[8] 1: bcd[9] 2: bcd[10] 3: bcd[11] 0: - 1: - 2: - 3: - millisecond counter; binary coded decimal value, high nibble regirqmask1 65 101 0000 0: maskirqpa[0] 1: maskirqpa[1] 2: maskirqpa[2] 3: maskirqpa[3] port a interrupt mask; masking active low regirqmask2 66 102 0000 0: maskirqpb0comp 1: maskirqblink 2: maskirqhz32/8 3: maskirqhz1 prescaler interrupt mask; masking active low regirqmask3 67 103 0000 0: maskirqcntcomp 1: maskirqcount0 2: maskirqmsc 3: maskirqvld 10 bit counter, millisecond counter, serial interrupt mask masking active low regirq1 68 104 0000 0: irqpa[0] 1: irqpa[1] 2: irqpa[2] 3:irqpa[3] 0: rirqpa[0] 1: rirqpa[1] 2: rirqpa[2] 3: rirqpa[3] read: port a interrupt write: reset if data bit = 1 regirq2 69 105 0000 0: irqpb0comp 1: irqblink 2: irqhz32/8 3: irqhz1 0: rirqpb0comp 1: rirqblink 2: rirqhz32/8 3: rirqhz1 read: prescaler irq ; write: reset if data bit = 1
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 41 www.emmicroelectronic.com register name add hex add dec reset value read bits write bits remarks b'3210 read / write bits regirq3 6a 106 0000 0:irqcntcomp 1: irqcount0 2: irqmsc 3: irqvld 0: rirqcntcomp 1: rirqcount0 2: rirqmsc 3: rirqvld read: 10 bit counter, millisecond counter, serial interrupt write: reset if data bit =1. regsyscntl1 6b 107 0000 0: chtmdis 1: selintfull 2: '0' 3: inten 0: chtmdis 1: selintfull 2: sleep 3: inten system control 1 chtmdis only usable for em test modes with test=1 regsyscntl2 6c 108 0p00 p=por 0: wdval0 1: wdval1 2: sleepen 3: '0' 0: -- 1: -- 2: sleepen 3: wdreset system control 2; watchdog value and periodical reset, enable sleep mode regpresc 6d 109 0000 0: debsel 1: printsel 2: '0' 3: pwmon 0: debsel 1: printsel 2: respresc 3: pwmon prescaler control; debouncer and prescaler interrupt select ixlow 6e 110 xxxx 0: ixlow[0] 1: ixlow[1] 2: ixlow[2] 3: ixlow[3] internal p index register low nibble; ixhigh 6f 111 xxxx 0: ixhigh[4] 1: ixhigh[5] 2: ixhigh[6] 3: '0' 0: ixhigh[4] 1: ixhigh[5] 2: ixhigh[6] 3: -- internal p index register high nibble; reglcdcntl1 71 113 --00 0: cktripsel0 1: cktripsel1 2: -- 3: -- lcd control 0 multiplier clock reglcdcntl2 72 114 111p p=por 0: lcdextsupply 1: lcd4xmux 2: lcdoff 3: lcdblank lcd control 1; main selects regvldcntl 73 115 0000 0: nologicwd 1: nooscwd 2: vldbusy 3: vldresult 0: nologicwd 1: nooscwd 2: vldstart 3: -- voltage level detector control p=por means that this bit is set to 0 on por only.
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 42 www.emmicroelectronic.com 14. option register memory map the values of the option registers are set by initial reset on power up and through write operations only. other resets as reset from watchdog, reset from input port a do not change the options register value. register name add hex add dec . power on value read bits write bits remarks b'3210 read / write bits optdebintpa opt[3:0] 75 117 0000 0: nodebintpa[0] 1: nodebintpa[1] 2: nodebintpa[2] 3: nodebintpa[3] option register; debouncer on port a for interrupt gen. default: debouncer on optintedgpa opt[7:4] 76 118 0000 0: intedgpa[0] 1: intedgpa[1] 2: intedgpa[2] 3: intedgpa[3] option register; interrupt edge select on port a default: pos. edge optnopullpa opt[11:8] 77 119 0000 0: nopullpa[0] 1: nopullpa[1] 2: nopullpa[2] 3: nopullpa[3] option register; pull-down selection on port a default: pull-down optnopdpb opt[15:12] 78 120 0000 0: nopdpb[0] 1: nopdpb[1] 2: nopdpb[2] 3: nopdpb[3] option register; pull-down selection on port b default: pull-down optnchopdpb opt[19:16] 79 121 0000 0: nchopdpb[0] 1: nchopdpb[1] 2: nchopdpb[2] 3: nchopdpb[3] option register; n-channel open drain output on port b default: cmos output optfselpb opt[31:28] 7b 123 0000 0: noinputreset 1: pb32khzout 2: pb2khzout 3: pb1hzout option register; port a input reset selection, frequency output on port b optinprsel1 7c 124 0000 0: inpres1pa[0] 1: inpres1pa[1] 2: inpres1pa[2] 3: inpres1pa[3] option register; port a input reset selection, refer to reset part optinprsel2 7d 125 0000 0: inpres2pa[0] 1: inpres2pa[1] 2: inpres2pa[2] 3: inpres2pa[3] option register; reset through port a inputs selection, refer to reset part regtestem 7f 127 ---- ---- accu for em test only; write accu on port b test = 1
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 43 www.emmicroelectronic.com 15. active supply current test for this purpose, five instructions at the end of the rom will be added. this will be done at em marin. so the user must keep must only use up to 1275 instructions. testloop: sti 00h, 0ah ldr 1bh nxorx jpz testloop jmp 00h to stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop: 1bh: 0101b 32h: 1010b 6eh: 0010b 6fh: 0011b free space after last instruction: jmp 00h (0000) remark: empty space within the program are filled with nop (foff).
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 44 www.emmicroelectronic.com 16. mask options most options which in many controllers are realized as metal mask options are directly user selectable with the option registers, therefore allowing a maximum freedom of choice .see chapter: 14. the following options can be selected at the time of programming the metal mask rom, except the lcd segment allocation which is defined using the interconnect metal2 mask. 16.1 input / output ports 16.1.1 port a metal options pull-up or no pull-up can be selected for each port a input. a pull-up selection is excluding a pull-down on the same input. pull-down (default) or no pull-down can be selected for each port a input. a pull-down selection is excluding a pull-up on the same input. the total pull value (pull-up or pull- down) is a series resistance out of the resistance r1 and the switching transistor. as a switching transistor the user can choose between a high impedance (weak) or a low impedance (strong) switch. weak, strong or none must be chosen. the default is strong. the default resistor r1 value is 100 kohm. the user may choose a different value from 150 kohm down to 0 ohm. however the value must first be checked and agreed by em microelectronic marin sa. refer also to chapter 17.2 and 17.3 for the pull values. to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull- down with r1=100 kohm to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull-up with r1=100 kohm figure 28. port a pull options resistor r1 mpapdweak[n] weak pull-down mpapdstrong[n] strong pull-down mpapuweak[n] weak pull-up mpapustrong[n] strong pull-up pull-up control pa[n] terminal 100 kohm no pull-up no pull-down pull-down control or input circuitry option name strong pull- down w pull- down r1 value typ.100k no pull- down 1 2 3 4 mpapd[3] pa3 input pull-down mpapd[2] pa2 input pull-down mpapd[1] pa1 input pull-down mpapd[0] pa0 input pull-down option name strong pull-up weak pull-up r1 value typ.100k no pull-up 1 2 3 4 mpapu[3] pa3 input pull-up mpapu[2] pa2 input pull-up mpapu[1] pa1 input pull-up mpapu[0] pa0 input pull-up
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 45 www.emmicroelectronic.com 16.1.2 port b metal options pull-up or no pull-up can be selected for each port b input. the pull-up is only active in nch. open drain mode. pull-down or no pull-down can be selected for each port b input. the total pull value (pull-up or pull- down) is a series resistance out of the resistance r1 and the switching transistor. as a switching transistor the user can choose between a high impedance (weak) or a low impedance (strong) switch. weak , strong or none must be chosen. the default is strong. the default resistor r1 value is 100 kohm. the user may choose a different value from 150 kohm down to 0 ohm. however the value must first be checked and agreed by em microelectronic marin sa. refer also to chapter 17.2 and 17.3 for the pull values. to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull- down with r1=100 kohm to select an option put an x in column 1,2 and 4 and reconfirm the r1 value in column 3. the default value is : strong pull-up with r1=100 kohm figure 29. port b pull options resistor r1 mpbpdweak[n] weak pull-down mpbpdstrong[n] strong pull-down mpbpuweak[n] weak pull-up mpbpustrong[n] strong pull-up pull-u p control pb[n] terminal 100 kohm pull-down control or block no pull-up no pull-down input circuitry option name strong pull- down weak pull- down r1 value typ.100k no pull- down 1 2 3 4 mpbpd[3] pb3 input pull-down mpbpd[2] pb2 input pull-down mpbpd[1] pb1 input pull-down mpbpd[0] pb0 input pull-down option name strong pull-up weak pull-up r1 value typ. 100k no pull-up 1 2 3 4 mpbpu[3] pb3 input pull-up mpbpu[2] pb2 input pull-up mpbpu[1] pb1 input pull-up mpbpu[0] pb0 input pull-up
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 46 www.emmicroelectronic.com 16.1.3 voltage regulator option by default the internal voltage regulator supplies the core logic the ram and the rom. with option mvreg(b) the regulator is cut and vbat is supplying the core logic the rom and the ram. 16.1.4 svld and input comp level option by default the level is 2.0 volts. the maximum value is 3.3 volt and the minimum is 1.2 volts. before choosing a value other than the default, please contact em microelectronic marin sa, to check for already existing levels. the chosen value is called v svldn om. 16.1.5 debouncer frequency option by default the debouncer frequency is ck[11]. the user may choose ck[14] instead of ck[11]. ck[14 ]corresponds to maximum 0.25ms debouncer time in case of a 32khz oscillator. 16.1.6 user defined lcd segment allocation if using a different segment allocation from the one described in chapter 0 , one needs to fill in the table below. the segment allocation connections are realized with the interconnect metal 2 mask. in case of 4 times mux com[1] com[2] com[3] com[4] in case of 3 times mux com[1] com[2] com[3] -- seg[1] seg[2] seg[3] seg[4] seg[5] seg[6] seg[7] seg[8] the customer should specify the required options at the time of ordering. a copy of the pages 44 to 46 as well as the ? software rom characteristic file ? generated by the assembler (*.sta) should be attached to the order. also the customer package marking, 7 characters, should be defined at that time. option name default value user value a b mvreg voltage regulator yes option name default value user value a b vsvld comparator level and svld level 2.0 option name default value user value a b mdeb debouncer freq. ck[11]
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 47 www.emmicroelectronic.com 17. temp. and voltage behaviors 17.1 idd current (typical) id d h alt m o d e; n o r eg ulat o r ; v d d =1.5v 0 250 50 0 750 -20 0 20 40 60 80 [c] [na ] id d halt m o d e lc d o n; n o r eg ulat o r ; v d d =1.5v 0 300 600 900 -20 0 20 40 60 80 [c] [na ] idd run m ode lcd on; no regulator ; vdd=1.5v 10 0 0 15 0 0 2000 2500 -20 0 20 40 60 80 [c] [na ] idd halt m ode; regulator; vdd=3.0v 0 250 50 0 750 -20 0 20 40 60 80 [c] [na ] idd halt m ode lcd on; regulator; vdd=3.0v 0 300 600 900 -20 0 20 40 60 80 [c] [na ] idd run m ode lcd on; regulator; vdd=3.0v 10 0 0 15 0 0 2000 2500 -20 0 20406080 [c] [na ] 17.2 pull-down resistance (typical) pulld o w n w eak; r eg ulato r; 2 5d eg 0 10 0 200 300 400 1. 4 2 2 .6 3 .2 [v ] [kohm] pulld o w n w eak; n o r eg ulato r; 2 5d eg 0 10 0 200 300 1.21.4 1.61.8 [v ] [kohm] pulldown w eak, regulator; vdd=3.0v 0 15 0 300 450 600 -20 0 20 40 60 80 [c] [kohm] pulldown w eak; no regulator; vdd=1.5v 0 50 10 0 15 0 200 -20 0 20 40 60 80 [c] [kohm] pulld o w n stro ng ; r eg ulato r; 2 5d eg 95 97.5 10 0 102.5 10 5 1.4 2 2 .6 3 .2 [v ] [kohm] pulldown strong; no regulator; 25deg 95 97.5 10 0 102.5 10 5 1.2 1. 4 1.6 1.8 [v ] [kohm] pulldown strong; regulator; vdd=3.0v 0 50 10 0 15 0 -20 0 20 40 60 80 [c ] [kohm] pulld o w n stro ng ; n o r eg ulato r; v d d =1.5v 0 50 10 0 15 0 -20 0 20 40 60 80 [c ] [kohm]
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 48 www.emmicroelectronic.com 17.3 pull-up resistance (typical) pullup st ro ng ; n o r eg ulato r; t emp =2 5d eg 80 10 0 12 0 14 0 1.2 1. 4 1. 6 1. 8 [v ] [kohm] pullup w eak; n o r eg ulat o r; t emp =2 5d eg 0 50 0 1000 15 0 0 2000 1.21.4 1.61.8 [v ] [kohm] pullup w eak; r eg ulato r; t emp =2 5d eg 0 50 0 10 0 0 15 0 0 2000 1.4 2 2 .6 3 . 2 [v ] [kohm] pullup st ro ng ; r eg ulat o r; t emp =2 5d eg 80 10 0 12 0 14 0 1.4 2 2 .6 3 . 2 [v ] [kohm] pullup w eak; n o r eg ulat o r; v d d =1.5v 400 600 800 10 0 0 -20 0 20 40 60 80 [c ] [kohm] pullup w eak; r eg ulat o r; v d d =3 .0 v 0 10 0 200 300 -20 0 20 40 60 80 [c ] [kohm] pullup strong ; regulator; v d d=3.0v 0 50 10 0 15 0 -20 0 20 40 60 80 [c ] [kohm] pullup strong; no regulator; vdd=1.5v 0 50 10 0 15 0 -20 0 20 40 60 80 [c ] [kohm] 17.4 output currents (typical) iol c urrent s; v d s=0 .15/ 0 .3 / 0 .5/ 1.0 v ; temp =2 5d eg 0.15 0.3 0.5 1. 0 0.0 3.0 6.0 9.0 12 . 0 15 . 0 1. 2 1. 8 2 . 4 3 3 . 6 [v] [ma] ioh c ur r ent s; v d s=0 .15/ 0 .3 / 0 .5/ 1.0 v ; temp =2 5d eg 0.15 0.3 0.5 1. 0 -12.0 -9.0 -6.0 -3.0 0.0 1.2 1.8 2.4 3 3.6 [v] [ma] ioh current s; v dd =1.5v ; v d s=0 .15/ 0 .3 / 0 .5/ 1.0 v 0.15 0.3 0.5 1. 0 -2.0 -1.5 -1.0 -0.5 0.0 -20 0 20 40 60 80 [c] [ma] iol current s; v dd =1.5v ; v d s=0 .15/ 0 .3 / 0 .5/ 1.0 v 0.15 0.3 0.5 1. 0 0.0 1. 0 2.0 3.0 4.0 5.0 -20 0 20 40 60 80 [c] [ma] ioh c ur rent s; v d d =3 .0 v ; v d s=0 .15/ 0 .3 / 0 .5/ 1.0 v 0.15 0.3 0.5 1. 0 -12.0 -9.0 -6.0 -3.0 0.0 -20 0 20 40 60 80 [c] [ma] iol c ur rent s; v d d =3 .0 v ; v d s=0 .15/ 0 .3 / 0 .5/ 1.0 v 0.15 0.3 0.5 1. 0 0.0 5.0 10 . 0 15 . 0 -20 0 20 40 60 80 [c] [ma]
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 49 www.emmicroelectronic.com 18. em6620 electrical specifications 18.1 absolute maximum ratings min. max. units power supply vdd-vss - 0.2 + 3.6 v input voltage vss - 0,2 vdd+0,2 v storage temperature - 40 + 125 c electrostatic discharge to mil-std-883c method 3015.7 with ref. to vss -2000 +2000 v maximum soldering conditions 10s x 250 c stresses above these listed maximum ratings may cause permanent damage to the device. exposure beyond specified electrical characteristics may affect device reliability or cause malfunction. 18.2 handling procedures this device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other cmos component. unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. 18.3 standard operating conditions parameter min typ max unit description temperature -20 25 85 c vdd_range1 1.4 3.0 3.6 v with internal voltage regulator vdd_range2 1.2 1.5 1.7 without internal voltage regulator vss 0 v reference terminal c vddca (note 1) 100 nf regulated voltage capacitor fq 32768 hz nominal frequency rqs 35 kohm typical quartz serial resistance cl 8.2 pf typical quartz load capacitance df/f +/- 30 ppm quartz frequency tolerance note 1: this capacitor filters switching noise from vdd to keep it away from the internal logic cells. in noisy systems the capacitor should be chosen bigger than minimum value. 18.4 dc characteristics - power supply conditions: vdd=1.5v, t=25c, without internal voltage regulator (unless otherwise specified) parameter conditions symbol min. typ. max. unit active supply current (note2,3) iv dda1 2.0 3.0 a (in active mode with lcd on) -20 ... 85c (note2,3) iv dda1 3.1 a standby supply current iv ddh1 0.4 0.6 a (in halt mode, lcdoff) -20 ... 85c iv ddh1 0.8 a sleep supply current iv dds1 0.1 0.25 a -20 ... 85c iv dds1 0.28 a por static level -20 ... 85c v por1 0.85 1.1 v ram data retention v rd1 1.0 v note 2: lcd display not connected. note 3: for test reasons, the user has to provide a test loop with successive writing and reading of two different addresses (5 instructions should be reserved for this measurement).
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 50 www.emmicroelectronic.com conditions: vdd=3.0v, t=25c, with internal voltage regulator (unless otherwise specified) parameter conditions symb. min. typ. max. unit active supply current (note2,3) iv dda2 2.1 3.1 a (in active mode with lcd on) -20 ... 85c (note2,3) iv dda2 3.5 a standby supply current iv ddh2 0.5 0.7 a (in halt mode, lcdoff) -20 ... 85c iv ddh2 0.9 a sleep supply current iv dds2 0.15 0.28 a -20 ... 85c iv dds2 0.3 a por static level -20 ... 85c, no load on vreg v por2 0.95 1.25 v ram data retention -20 ... 85c v rd2 1.2 v regulated voltage halt mode, no load v reg 1.2 1.4 1.7 v note 2: lcd display not connected. note 3: for test reasons, the user has to provide a test loop with successive writing and reading of two different addresses (5 instructions should be reserved for this measurement). 18.5 svld and input comparator conditions: standard operating conditions (unless otherwise specified) parameter conditions symb. min. typ. max. unit svld voltage level -10 ... 60 c v svld 0.92 v svldn om v svld nom 1.08 v svldn om v -20 ... 85 c v svld 0.9 v svldn om v svld nom 1.1 v svldn om v input comparator -10 ... 60 c v svld 0.92 v svldn om v svld nom 1.08 v svldn om v vinmax=vdd+0.2v vdd= v svldn om -20 ... 85 c v svld 0.9 v svldn om v svld nom 1.1 v svldn om v input comparator voltage dependency versus vdd -20 ... 85 c dvsvld/dvdd -100 mv/v note 4: vsvldnom is coming from the svld option mask definition sheet (chapter 16.1.4). 18.6 oscillator conditions: t=25 c (unless otherwise specified) parameter conditions symb. min. typ. max. unit temperature stability +15 ... +35 c df/f x dt 0,3 ppm /c voltage stability (note 5) vdd=1,4 - 1,6 v df/f x du 5 ppm /v input capacitor ref vss cin 5,6 7 8,4 pf output capacitor ref vss cout 12,1 14 15,9 pf transconductance 50mvpp,vddmin gm 2.5 15.0 a/v oscillator start voltage tstart < 10 s ustart vddmin v oscillator start time vdd > vddmin tdosc 0.5 3 s system start time (oscillator + cold start + reset) tdsys 1.5 4 s oscillation detector frequency vdd > vddmin t detfreq 12 khz note 5 ; applicable only for the versions without the internal voltage regulator
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 51 www.emmicroelectronic.com 18.7 dc characteristics - i/o pins conditions: t= -20 ... 85 c (unless otherwise specified) vdd=1.5v means; measures without voltage regulator vdd=3.0v means; measures with voltage regulator parameter conditions symb min. typ. max. unit input low voltage ports a,b test vdd < 1.5v v il vss 0.2vdd v ports a,b test vdd > 1.5v v il vss 0.3vdd v qin with regulator v il vss 0.1vreg v qin without regulator v il vss 0.1vdd v qout (note 7) input high voltage ports a,b test v ih 0.7vdd vdd v qin with regulator v ih 0.9vreg vreg v qin without regulator v ih 0.9vdd vdd v qout (note 7) output low current vdd=1.5v , vol=0.15v i ol 1.1 ma port b vdd=1.5v , vol=0.30v i ol 2.1 ma vdd=1.5v , vol=0.50v i ol 1.55 3.1 ma vdd=3.0v , vol=0.15v i ol 1.8 ma vdd=3.0v , vol=0.30v i ol 3.6 ma vdd=3.0v , vol=0.50v i ol 5.8 ma vdd=3.0v , vol=1.00v i ol 5.5 11.0 ma output high current vdd=1.5v, voh= vdd-0.15v i oh -0.6 ma port b vdd=1.5v, voh= vdd-0.30v i oh -1.1 ma vdd=1.5v, voh= vdd-0.50v i oh -1.5 -0.75 ma vdd=3.0v, voh= vdd-0.15v i oh -1.3 ma vdd=3.0v , voh= vdd-0.30v i oh -2.6 ma vdd=3.0v , voh= vdd-0.50v i oh -4.2 ma vdd=3.0v , voh= vdd-1.00v i oh -7.7 -3.85 ma input pull-down vdd=1.5v, pin at 1.5v, 25 c r pd 15k ohm test vdd=3.0v, pin at 3.0v, 25 c r pd 15k ohm input pull-down vdd=1.5v, pin at 1.5v, 25 c r pd 100k 150k 300k ohm port a,b (note 8) weak vdd=3.0v, pin at 3.0v, 25 c r pd 200k 300k 600k ohm input pull-up vdd=1.5v, pin at 0.0v, 25 c r pu 500k 800k 2000k ohm port a,b (note 8) weak vdd=3.0v, pin at 0.0v, 25 c r pu 115k 190k 475k ohm input pull-down vdd=1.5v, pin at 1.5v, 25 c r pd 72k 102k 132k ohm port a,b (note 8) strong vdd=3.0v, pin at 3.0v, 25 c r pd 70k 100k 130k ohm input pull-up vdd=1.5v, pin at 0.0v, 25 c r pu 76k 109k 142k ohm port a,b (note 8) strong vdd=3.0v, pin at 0.0v, 25 c r pu 72k 103k 134k ohm note 7 ; qout (osc2) is used only with quartz. note 8 : weak or strong are standing for weak pull resp. strong pull transistor. values are for r1=100kohm
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 52 www.emmicroelectronic.com 18.8 lcd seg[8:1] outputs conditions: t=25 c (unless otherwise specified) parameter conditions symb. min. typ. max. unit driver impedance level 0 iout = 5 a, ext. supply r segvl0 20 kohm driver impedance level 1 iout = 5 a, ext supply r segvl1 20 kohm driver impedance level 2 iout = 5 a, ext supply r segvl2 20 kohm driver impedance level 3 iout = 5 a, ext supply r segvl3 20 kohm 18.9 lcd com[4:1] outputs conditions: t=25 c (unless otherwise specified) parameter conditions symb. min. typ. max. unit driver impedance level 0 iout = 5 a, ext. supply r comvl0 10 kohm driver impedance level 1 iout = 5 a, ext. supply r comvl1 10 kohm driver impedance level 2 iout = 5 a, ext supply r comvl2 10 kohm driver impedance level 3 iout = 5 a, ext supply rcomvl3 10 kohm 18.10 dc output component conditions: t=25 c (unless otherwise specified) parameter conditions symb. min. typ. max. unit dc output component no load v dc_com 20 mv 18.11 lcd voltage multiplier conditions: t=25 c, vdd=vddtyp, all multiplier capa?s 100nf, multiplier freq=512hz. (unless otherwise specified) parameter conditions symb. min. typ. max. unit voltage bias level 1 1 a load v vl1 0.95 1.05 1.15 v voltage bias level 2 1 a load v vl2 2.10 v voltage bias level 3 1 a load v vl3 3.15 v temp dependency v v l1 1 a load, -10...60 c dv vl1 /dt -4.9 mv/c
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 53 www.emmicroelectronic.com 19. pad location diagram
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 54 www.emmicroelectronic.com 20. package & ordering information figure 32 tqfp32 package dimensions d d1 a e see detail "b" package outline, tqfp, 7 x 7 mm body, 1.00/0.10 mm form, 1.00 mm thick top view b see detail "a" e odd lead sides even lead sides detail "a" all dimensions in millimeters 0.30 min. 0.95 0.05 0.45 e n b l a 1 a d d 2 1 a o l y m b 32 0.80 bsc 0.37 0.60 0.45 0.75 7.00 bsc. 9.00 bsc. 1.00 typ. 0.15 1.05 1.20 max. tqfp32 s a1 a2 l detail "b" 1.00 ref. 0.20 min. 0.08 r. min. 0-7 0 min. 0.08/0.20 r.
em6620 ? em microelectronic-marin sa, 01/99, rev. d/254 55 figure 31 tqfp44 package dimensions d d1 a e see detail "b" package outline, tqfp, 10x10 mm body, 1.00/0.10 mm form, 1.4 mm thick top view b see detail "a" e odd lead sides even lead sides detail "a" all dimensions in millimeters 0.30 min. 0.05 0.45 e n b l a 1 a d d 2 1 a o l y m b 44 0.80 bsc 0.37 0.60 0.45 0.75 1.4 typ. max. tqfp44 s a1 a2 l detail "b" 1.00 ref. 0.20 min. 0.08 r. min. 0-7 0 min. 0.08/0.20 r. 12.00 bsc. 10.00 bsc. 0.15 1.6 1.45
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 56 www.emmicroelectronic.com 20.1 ordering information ordering part number (selected examples) part number package/die form delivery form/thickness em6620%%%tq32b tqfp 32 pin tape&reel em6620%%%tq32d tqfp 32 pin trays (plate) em6620%%%tq44b tqfp 44 pin tape&reel em6620%%%tq44d tqfp 44 pin trays (plate) em6620%%%ws11 sawn wafer 11 mils em6620%%%wp11 die in waffle pack 11 mils em6620%%%ww27 unsawn wafer 27 mils please make sure to give the complete part number when ordering, including the 3-digit version. the version is made of 3 digits %%%: the first one is a letter and the last two are numbers, e.g. c05 , c12, p20, etc. 20.2 package marking tqfp44 marking: tqfp32 marking: first line: em6620 0 %%y em6 6 2 0 # second line: p p p pppppppp p p p p p p p third line: ccccccccccc c c c c c y p where: %% = last two-digits of the customer-specific number given by em (e.g. 05, 12, 20, etc.) # = last digit of the customer-specific number given by em (e.g. 2, 4, 6, 8) y = year of assembly pp?p = production identification (date & lot number) of em microelectronic cc?c = customer specific package marking on third line, selected by customer 20.3 customer marking there are 11 digits available for customer marking on tqfp44 . there are 5 digits available for customer marking on tqfp32 . please specify below the desired customer marking. em microelectronic-marin sa cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an em microelectronic-marin sa product. em microelectronic-marin sa reserves the right to change the circuitry and specifications without notice at any time. you are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. packaged device: device in die form: customer version: customer version: customer-s p ecific numbe r customer-s p ecific numbe r given by em microelectronic given by em microelectronic packa g e: die form: tq32 = tqfp 32 p in ww = wafe r tq44 = tqfp 44 p in ws = sawn wafer/frame wp = waffle pack thickness: deliver y form: 11 = 11 mils ( 280um ) , b y default b = ta p e&reel 27 = 27 mils ( 686um ) , not backla pp ed d = trays (plate) (for other thickness, contact em) em6620 %%% ws 11 em6620 %%% tq32 b
em6620 03/02 rev. f/443 copyright ? 2002, em microelectronic-marin sa 57 www.emmicroelectronic.com 21. spec. update date ,name version chapter concerned old text new text 20/11/97 , jag b/156, oct 97 5.2 debouncer times are 2ms resp 0.5ms debouncer times are 2ms resp 0.25ms 20/11/97 , jag 6.2.1 this means a worst case of 16ms(default) or 2ms (0.5ms) by this means a worst case of 16ms(default) or 2ms (0.25ms) by 20/11/97 , jag 16.1.5 ck[14] corresponds to a maximum 0.5ms debouncing ck[14] corresponds to a maximum 0.5ms debouncing 20/11/97 , jag all new pagination 19/12/97, jag msc - new detailed description + 1page 03/02/98, jag 1.0 - added marking for mfp programming 16/02/98, jag 7.0 - - included default marking for up/down count mode and load command 24/3/98, jag 7.5.1 - added < for limited pulse generation one must load the complementary pulse number value. i.e for 5 pulses counting on 4 bits load bits[9 :4] with hex 3a (bin 111010).> 24/3/98, jag 7.4 7.5 in 7.4 removed the phrase < one must not use a compare value of hex 0 in upcount mode nor a value of hex 3ff (resp ff,3f, f if limited bit compare) in downcount mode.> in 7.5 added the phrase 18.6.98, jag c/227, june 98 all new version in doc control spelling corrections, figure updates, added die size and package drawings 8.12.98 jag 10 svld level select in in regsvldl svld level select in in regsvldl 8.12.98 jag 21 tqfp44 thickness 1.0mm tqfp44 thickness 1.4mm 20.1.99 jag d/254 feb 99 22 - added the ordering information for packaged devices inclusive device marking and also ordering info for dies. 19.09.01 div e/375 sept 01 15 new testloop 19.09.01 div e/375 sept 01 18.4 ivdda, ivddh, ivdds max. over temperature change in 18.4 dc characteristics. 18.4 dc characteristics - power supply pins - new values for ivdda, ivddh, ivdds max. 01.11.01 pert e/375 all - change header & footer, add url mention 22.03.02 19 & 22 - change pad location diagram & ordering information em microelectronic-marin sa cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an em microelectronic-marin sa product. em microelectronic-marin sa reserves the right to change the circuitry and specifications without notice at any time. you are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.

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